JPS59161840A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To flatten the surface of a substrate as well as to enhance the moisture-resisting property by a method wherein when a multilayer interconnection is provided on the semiconductor substrate, whereon a semiconductor element has been formed, through an insulating film, a two-layer structural insulating film, whose underlayer is an organic insulating film and top layer is an inorganic insulating film, is used as the interlayer insulating film. CONSTITUTION:An insulating film 2 consisting of SiO2 or Si3N4 is coated on an Si substrate 1, an opening is bored and an Al wiring 3 of the first layer is extendedly formed on the film 2 while being made to abut on the substrate 1. Then, an interlayer insulating film is provided on the whole surface including the Al wiring 3. At this time, the interlayer insulating film is made into a double-layer structure, whose underlayer is a polyimide film 4 and top layer is a plasma SiO film 5. After that, a through hole 6 is bored on the films 5 and 4 in such a way as to interpenetrate the parts of the films 5 and 4, which commonly correspond to a prescribed position on the wiring 3 and is made to contact to the exposed wiring 3, and an Al wiring 7 of the second layer is coated on the film 5. Through these procedures, the surface step parts are flattened by using the film 4 and infiltration of water content is prevented by the film 5. This results in protecting the wiring 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a multilayer wiring structure in a semiconductor integrated circuit device (hereinafter abbreviated as IC) in which a polyimide-based organic insulating film is used as an insulating film between wiring layers.

[Background technology]

In recent ICs, a multilayer wiring structure in which wiring is multilayered and an insulating film is provided between the wiring layers is common.

The insulating film between the wiring layers must be sufficiently thick in order to prevent the occurrence of A4 hillocks and the like and to eliminate steps caused by the underlying wiring, and must also have a certain degree of heat resistance. The present inventor has developed a three-layer structure of (1) polyimide resin or (2) plasma-based silicon compound/5OG (spin-on glass)/PSG (phosphorus silicate glass) as an insulating film that meets this requirement. I am using it.

Regarding (1) above, polyimide resin has high heat resistance and is thick, so it can be expected to flatten the surface, but microfabrication for forming through holes etc. is difficult, and when making a resin sealed package, The problem is that it has poor heat resistance against moisture entering the resin or from the outside.

Regarding (2) above, in particular, the upper layer of low-pressure plasma-based silicon compounds (P-8iN or P-8iO) has advantages such as high mechanical strength, is difficult to crack, and does not absorb moisture, but it is difficult to process. IC is MO
When 8 elements are included, when depositing SiO or the like using Goodsma, a problem arises in that the thin (in the case of 500 A or less) SiO2 film of the MO8 element is destroyed.

[Purpose of the invention]

The present invention improves the electrode structure in order to solve the above problems, and aims to provide a highly reliable and miniaturized IC.

[Summary of the invention]

To briefly explain the outline of a representative invention among the inventions disclosed in this application, in a semiconductor device having multilayer wiring, the first layer (lower layer) is made of an organic material such as a polyimide resin in an insulating film between the multilayer wiring layers. As an insulating film, the second layer (upper layer)
By using an insulating film with a two-layer structure such as an inorganic insulating film such as a silicon compound film using low-pressure plasma, 1
The object of the invention is achieved by flattening the surface with the polyimide resin layer and improving moisture resistance with the plasma silicon compound layer.

〔Example〕

FIGS. 1 to 3 are cross-sectional views showing one embodiment of the multilayer wiring structure according to the present invention according to a part of the process. An insulating film 2 made of an oxide film (Sin2 film) or PSG (phosphosilicate glass) was formed on the surface of a semiconductor substrate 1, and a part of the insulating film 2 was contact photoetched to form a first layer M (aluminum wiring) 3. On top of this, apply a liquid polyimide resin such as polyimide isoindoroquinazolinedione dissolved in an organic solvent sufficiently thickly using a spin coating method or the like to flatten the surface. By baking, a polyimide resin film with a thickness of about 2 μm is formed.

(b) Sin is deposited on the entire surface in low pressure plasma to form a plasma SiO film 5 with a thickness of about 1500 Å as shown in FIG.

(C) A photoresist mask (not shown) is provided to form through holes 6 between wirings, and carbon is removed in plasma.
Using F4 as an etchant, a part of the plasma SiO film 5 is opened, and then, using this plasma SiO film as a mask, a part of the polyimide resin is etched with a hydrazine solution to form a through hole reaching the first layer Al wiring 3. Open.

Finally, A4 is deposited and patterned and etched to form the second layer A (wiring) as shown in FIG.

This first layer Al wiring 7 is connected to the first layer A through a through hole.
l Connect the wiring.

According to such an embodiment, the insulating film between the two wiring layers is P.
It has a two-layer structure of -8iO/polyimide, and the first layer of polyimide resin can flatten the stepped portion of the surface, making it easy to microfabricate through holes, and the second layer of plasma SiO The first layer A [has the effect of protecting wiring.

FIG. 4 shows an embodiment in which the present invention is applied to a bipolar CMO8IC, with a sectional view of the essential parts thereof.

In the same figure, I is a bipolar transistor section, and ■ is a CM.
This is the O8FET section. The individual components are as follows.

11 is a p-type Si substrate (substray), 12 is an n
13 is an n-type epitaxial Si layer, 14 is a p-type buried layer.
A type well, 15 is type 1 isolation, and 16 is an isoplanar oxide film. On the bipolar side 17 is n
pn) n+ type collector of the transistor, 18 is the same p type space, 19 is the same n+ type emitter, 20 is the first layer A [wiring, 21 is the polyimide resin film, 22 is the plasma SiO film] , 23 are second layer A4 wirings that contact the collector.

On the 0MO8 side (II), 24 is a gate insulating film, 2
5 is a gate, 26 is a p-type source/drain, 27 is an n
Type source/drain 28 is a second layer A4 wiring that makes ohmic contact with the source/drain.

In the above embodiment, the gate insulating film 24 in the MOSFET is covered with the first layer of polyimide resin film 21 during plasma SiO formation of the interlayer insulating film, so gate dielectric breakdown due to plasma treatment can be avoided, and the interlayer insulating film The two-layer structure ensures a flat surface and moisture resistance.

〔effect〕

By forming the interlayer insulating film into a two-layer structure as described in the above embodiments, it is possible to provide a miniaturized and highly reliable IC.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above embodiments and can be modified in various ways without departing from the spirit thereof.

For example, 5iN (for example, Si, N, etc.) may be provided by plasma treatment on the second layer insulation film among the plurality of interlayer insulation films.

[Application field]

The present invention has a multilayer wiring structure and requires microfabrication.
It is suitable for resin-sealed semiconductor devices.

[Brief explanation of drawings]

1 to 3 are process cross-sectional views showing an example of a semiconductor device having a multilayer wiring structure according to the present invention through its manufacturing process. FIG. 4 is a sectional view of a main part of an example of a bipolar CMO8 IC having a multilayer wiring structure according to the present invention. 1... Silicon substrate, 2... Insulating film (Sin, film)
, 3... First layer A8 wiring, 4... Lower layer of interlayer insulating film (polyimide resin), 5... Upper layer (plasma 5 inch
), 6... Through hole, 7... Second layer AJJiJ
! .

Claims (1)

[Claims] 1.-Semiconductor substrate 1 with a semiconductor element formed on its main surface
In a semiconductor integrated circuit device in which multilayer wiring is provided on the body surface, an insulating film having a two-layer structure in which a lower layer is an organic insulating film and an upper layer is an inorganic insulating film is used as an insulating film between the multilayer wiring layers. A semiconductor integrated circuit device characterized by: 2. The semiconductor integrated circuit device according to claim 1, wherein at least a portion of the semiconductor element is an insulated gate type semiconductor element.