JPH05251573A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05251573A JPH05251573A JP4047276A JP4727692A JPH05251573A JP H05251573 A JPH05251573 A JP H05251573A JP 4047276 A JP4047276 A JP 4047276A JP 4727692 A JP4727692 A JP 4727692A JP H05251573 A JPH05251573 A JP H05251573A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon nitride
- insulating film
- interlayer insulating
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に利用さ
れ、特に、多層配線構造を持つ半導体素子のアルミニウ
ム配線間の層間絶縁膜の構造を改善した半導体装置に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an improved structure of an interlayer insulating film between aluminum wirings of a semiconductor element having a multilayer wiring structure.
【０００２】[0002]
【従来の技術】従来の素子上層部にボンディングパッド
を有するアルミニウム２層構造のトランジスタにおい
て、第一のアルミニウム配線と第二のアルミニウム配線
との間の層間膜構造について、図３を用いて説明する。2. Description of the Related Art In a conventional transistor having a two-layer aluminum structure having a bonding pad in the upper layer of an element, an interlayer film structure between a first aluminum wiring and a second aluminum wiring will be described with reference to FIG. .
【０００３】図３は従来のトランジスタ要部を示す縦断
面図である。ベース２、エミッタ３およびシリコン窒化
膜５上に第一のアルミニウム配線６を形成した後、プラ
ズマＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏ
ｓｉｔｉｏｎ）法によりプラズマシリコン窒化膜７を形
成する。次にフォトリソグラフィ技術およびエッチング
技術によってプラズマシリコン窒化膜７に第一のアルミ
ニウム膜６と第二のアルミニウム配線１０の導通部とな
るスルーホールを開口し、第二のアルミニウム配線１０
を形成させ、その上においてボンディング線１１をボン
ディングし、アルミニウム層構造のトランジスタを形成
していた。FIG. 3 is a vertical sectional view showing a main part of a conventional transistor. After forming the first aluminum wiring 6 on the base 2, the emitter 3 and the silicon nitride film 5, plasma CVD (Chemical Vapor Depo) is performed.
Then, the plasma silicon nitride film 7 is formed according to the position method. Next, a through hole which serves as a conduction part between the first aluminum film 6 and the second aluminum wiring 10 is opened in the plasma silicon nitride film 7 by photolithography technology and etching technology, and the second aluminum wiring 10 is formed.
Was formed and the bonding wire 11 was bonded thereon to form a transistor having an aluminum layer structure.
【０００４】[0004]
【発明が解決しようとする課題】この従来のプラズマＣ
ＶＤ法によって成長させたシリコン窒化膜一層を層間絶
縁膜として使用する方法では、３０μｍ以上の太さをも
つボンディング線を使った場合、ボンディング時のダメ
ージにより層間絶縁膜にクラックが発生し、ショート不
良の原因となり、信頼性を低下させる欠点があった。This conventional plasma C
In the method of using one layer of the silicon nitride film grown by the VD method as an interlayer insulating film, when a bonding wire having a thickness of 30 μm or more is used, cracks occur in the interlayer insulating film due to damage during bonding, and a short circuit failure occurs. However, there is a drawback that the reliability is lowered.
【０００５】本発明の目的は、前記の欠点を除去するこ
とにより、ボンディング時における層間絶縁膜のクラッ
クの発生を防止できる構造を有する半導体装置を提供す
ることにある。An object of the present invention is to provide a semiconductor device having a structure capable of preventing the generation of cracks in an interlayer insulating film during bonding by eliminating the above-mentioned drawbacks.
【０００６】[0006]
【課題を解決するための手段】本発明は、第一の金属配
線と、この第一の金属配線上に形成された層間絶縁膜
と、この層間絶縁膜上に形成された第二の金属配線とを
有する半導体装置において、前記層間絶縁膜中に形成さ
れた有機絶縁膜を有することを特徴とする。The present invention is directed to a first metal wiring, an interlayer insulating film formed on the first metal wiring, and a second metal wiring formed on the interlayer insulating film. And a semiconductor device having an organic insulating film formed in the interlayer insulating film.
【０００７】また、本発明は、前記層間絶縁膜はプラズ
マＣＶＤ法によって形成されたシリコン窒化膜であり、
前記有機絶縁膜はポリイミド樹脂膜であることが好まし
い。According to the present invention, the interlayer insulating film is a silicon nitride film formed by a plasma CVD method,
The organic insulating film is preferably a polyimide resin film.
【０００８】[0008]
【作用】層間絶縁膜としての例えばプラズマＣＶＤ法に
よるプラズマシリコン窒化膜中に、有機絶縁膜として例
えばポリイミド樹脂膜を形成する。Function: For example, a polyimide resin film is formed as an organic insulating film in a plasma silicon nitride film formed by plasma CVD as an interlayer insulating film.
【０００９】この構造によると、ボンディング時のダメ
ージはポリイミド樹脂層に吸収されて、プラズマシリコ
ン窒化膜の上面から下面に至るクラックの発生はなくな
り、信頼性を向上させることができる。According to this structure, the damage at the time of bonding is absorbed by the polyimide resin layer, the cracks from the upper surface to the lower surface of the plasma silicon nitride film are not generated, and the reliability can be improved.
【００１０】[0010]
【実施例】以下、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１１】図１は本発明の第一実施例としてのトラン
ジスタの要部を示す縦断面図である。FIG. 1 is a vertical sectional view showing a main part of a transistor as a first embodiment of the present invention.
【００１２】本第一実施例は、第一の金属配線としての
第一のアルミニウム配線６と、この第一のアルミニウム
配線６の上に形成された層間絶縁膜としてのプラズマＣ
ＶＤ法により形成された第一および第二のプラズマシリ
コン窒化膜７および９と、この第二のプラズマシリコン
窒化膜９上に形成された第二のアルミニウム配線１０と
を有するトランジスタにおいて、本発明の特徴とすると
ころの、プラズマシリコン窒化膜７とプラズマシリコン
窒化膜９間に形成された有機絶縁膜としてのポリイミド
膜８を有している。なお、ここで、プラズマシリコン窒
化膜９はポリイミド膜８を挿入するために特に形成され
たものである。In the first embodiment, a first aluminum wiring 6 as a first metal wiring and a plasma C as an interlayer insulating film formed on the first aluminum wiring 6 are formed.
In the transistor having the first and second plasma silicon nitride films 7 and 9 formed by the VD method and the second aluminum wiring 10 formed on the second plasma silicon nitride film 9, It has a characteristic polyimide film 8 as an organic insulating film formed between the plasma silicon nitride film 7 and the plasma silicon nitride film 9. Here, the plasma silicon nitride film 9 is formed especially for inserting the polyimide film 8.
【００１３】なお、図１において、１はコレクタ（シリ
コン基板）、２はベース、３はエミッタ、４はシリコン
酸化膜、５はシリコン窒化膜、および１１はボンディン
グ線である。In FIG. 1, 1 is a collector (silicon substrate), 2 is a base, 3 is an emitter, 4 is a silicon oxide film, 5 is a silicon nitride film, and 11 is a bonding line.
【００１４】次に、本第一実施例の製造方法の概要につ
いて説明する。Next, an outline of the manufacturing method of the first embodiment will be described.
【００１５】図１に示すように、ベース２およびエミッ
タ３上に形成されたシリコン酸化膜４の全面をＣＶＤ法
により成長させたシリコン窒化膜５によって被覆する。
その上に第一のアルミニウム配線６を１．０μｍ程度形
成し、その後プラズマＣＶＤ法によってプラズマシリコ
ン窒化膜７を５０００Å程度を成長させる。その上にボ
ンディング時のダメージを吸収することを目的とするポ
リイミド膜８を１．０μｍ程度形成し、さらに、その上
に再度プラズマＣＶＤ法によってプラズマシリコン窒化
膜９を１．５μｍ程度成長させる。その後、フォトリソ
グラフィ技術、およびエッチング技術によって、アルミ
ニウム層間絶縁膜であるプラズマシリコン窒化膜７、ポ
リイミド膜８、およびプラズマシリコン窒化膜９にアル
ミニウム配線６とアルミニウム配線１０の導通部となる
スルーホールを開口し、第二のアルミニウム配線１０を
２．０μｍ程度形成する。最後にボンディング線１１を
ボンディングする。As shown in FIG. 1, the entire surface of the silicon oxide film 4 formed on the base 2 and the emitter 3 is covered with a silicon nitride film 5 grown by the CVD method.
A first aluminum wiring 6 is formed thereon to have a thickness of about 1.0 μm, and then a plasma silicon nitride film 7 is grown to a thickness of about 5000 Å by plasma CVD. A polyimide film 8 for absorbing damage during bonding is formed thereon with a thickness of about 1.0 μm, and a plasma silicon nitride film 9 is further grown thereon with a thickness of about 1.5 μm by the plasma CVD method. After that, a through hole serving as a conductive portion between the aluminum wiring 6 and the aluminum wiring 10 is opened in the plasma silicon nitride film 7, the polyimide film 8 and the plasma silicon nitride film 9 which are aluminum interlayer insulating films by photolithography and etching techniques. Then, the second aluminum wiring 10 is formed to have a thickness of about 2.0 μm. Finally, the bonding wire 11 is bonded.
【００１６】図２は本発明の第二実施例の要部を示す縦
断面図である。本第二実施例では、プラズマＣＶＤ法に
より成長させた５０００Å程度のプラズマシリコン窒化
膜７上にポリイミド膜８を１．０μｍ程度形成した後、
フォトリソグラフィ技術とエッチング技術により部分的
にポリイミド膜８を除去し、プラズマＣＶＤ法によりプ
ラズマシリコン窒化膜９を１．５μｍ程度を成長させ
る。その後、フォトリソグラフィ技術、およびエッチン
グ技術によって層間絶縁膜に第一のアルミニウム配線６
と第二のアルミニウム配線１０の導通部となるスルーホ
ールを開口し、第二のアルミニウム配線１０を形成す
る。FIG. 2 is a longitudinal sectional view showing the main part of the second embodiment of the present invention. In the second embodiment, after forming a polyimide film 8 of about 1.0 μm on the plasma silicon nitride film 7 of about 5000 Å grown by the plasma CVD method,
The polyimide film 8 is partially removed by the photolithography technique and the etching technique, and the plasma silicon nitride film 9 is grown to a thickness of about 1.5 μm by the plasma CVD method. After that, the first aluminum wiring 6 is formed on the interlayer insulating film by photolithography and etching.
Then, a through hole serving as a conductive portion of the second aluminum wiring 10 is opened to form the second aluminum wiring 10.
【００１７】本第二実施例は、ボンディング時のダメー
ジの吸収を要所ごとに設けた、本発明の特徴とする、ポ
リイミド膜８で吸収できるようにしたものである。In the second embodiment, the absorption of the damage at the time of bonding is provided at every important point, which is a feature of the present invention and can be absorbed by the polyimide film 8.
【００１８】[0018]
【発明の効果】以上説明したように、本発明は、第一の
アルミニウム配線と第二のアルミニウム配線の層間絶縁
膜であるプラズマＣＶＤ法によって成長させたプラズマ
シリコン窒化膜の間に例えばポリイミド樹脂膜を形成す
ることによって、ボンディングのダメージを吸収し、層
間絶縁膜のクラックによるショート不良の発生を防止し
信頼性を向上できる効果がある。As described above, according to the present invention, for example, a polyimide resin film is provided between the plasma silicon nitride film grown by the plasma CVD method which is the interlayer insulating film of the first aluminum wiring and the second aluminum wiring. By forming the film, it is possible to absorb the damage of bonding, prevent the occurrence of short circuit defects due to cracks in the interlayer insulating film, and improve the reliability.
【図１】本発明の第一実施例の要部を示す縦断面図。FIG. 1 is a longitudinal sectional view showing a main part of a first embodiment of the present invention.
【図２】本発明の第二実施例の要部を示す縦断面図。FIG. 2 is a vertical cross-sectional view showing a main part of a second embodiment of the present invention.
【図３】従来例の要部を示す縦断面図。FIG. 3 is a vertical cross-sectional view showing a main part of a conventional example.
１ コレクタ ２ ベース ３ エミッタ ４ シリコン酸化膜 ５ シリコン窒化膜 ６、１０ アルミニウム配線 ７、９ プラズマシリコン窒化膜 ８ ポリイミド膜 １１ ボンディング線 1 Collector 2 Base 3 Emitter 4 Silicon Oxide Film 5 Silicon Nitride Film 6, 10 Aluminum Wiring 7, 9 Plasma Silicon Nitride Film 8 Polyimide Film 11 Bonding Line
Claims (2)
上に形成された層間絶縁膜と、この層間絶縁膜上に形成
された第二の金属配線とを有する半導体装置において、 前記層間絶縁膜中に形成された有機絶縁膜を有すること
を特徴とする半導体装置。1. A semiconductor device comprising: a first metal wiring; an interlayer insulating film formed on the first metal wiring; and a second metal wiring formed on the interlayer insulating film. A semiconductor device having an organic insulating film formed in an interlayer insulating film.
って形成されたシリコン窒化膜であり、前記有機絶縁膜
はポリイミド樹脂膜である請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the interlayer insulating film is a silicon nitride film formed by a plasma CVD method, and the organic insulating film is a polyimide resin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4047276A JPH05251573A (en) | 1992-03-04 | 1992-03-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4047276A JPH05251573A (en) | 1992-03-04 | 1992-03-04 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05251573A true JPH05251573A (en) | 1993-09-28 |
Family
ID=12770769
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4047276A Pending JPH05251573A (en) | 1992-03-04 | 1992-03-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05251573A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6538326B2 (en) | 2000-10-16 | 2003-03-25 | Sharp Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| SG128464A1 (en) * | 2004-04-30 | 2007-01-30 | Advanced Chip Eng Tech Inc | Structure of package |
-
1992
- 1992-03-04 JP JP4047276A patent/JPH05251573A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6538326B2 (en) | 2000-10-16 | 2003-03-25 | Sharp Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| SG128464A1 (en) * | 2004-04-30 | 2007-01-30 | Advanced Chip Eng Tech Inc | Structure of package |
| US7259468B2 (en) * | 2004-04-30 | 2007-08-21 | Advanced Chip Engineering Technology Inc. | Structure of package |
| CN100447994C (en) * | 2004-04-30 | 2008-12-31 | 育霈科技股份有限公司 | Structure of package |
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