DE69216752T2 - Verfahren zur Herstellung einer Halbleiter-Scheibe - Google Patents

Verfahren zur Herstellung einer Halbleiter-Scheibe

Info

Publication number
DE69216752T2
DE69216752T2 DE1992616752 DE69216752T DE69216752T2 DE 69216752 T2 DE69216752 T2 DE 69216752T2 DE 1992616752 DE1992616752 DE 1992616752 DE 69216752 T DE69216752 T DE 69216752T DE 69216752 T2 DE69216752 T2 DE 69216752T2
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor wafer
wafer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE1992616752
Other languages
English (en)
Other versions
DE69216752D1 (de
Inventor
Takao Otokawa
Nobuhiro Isuda
Satoshi Ushio
Takao Takenaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=17739480&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69216752(T2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of DE69216752D1 publication Critical patent/DE69216752D1/de
Application granted granted Critical
Publication of DE69216752T2 publication Critical patent/DE69216752T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02—Heat treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
DE1992616752 1991-10-07 1992-10-02 Verfahren zur Herstellung einer Halbleiter-Scheibe Expired - Fee Related DE69216752T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3289155A JP2758093B2 (ja) 1991-10-07 1991-10-07 半導体ウェーハの製造方法

Publications (2)

Publication Number Publication Date
DE69216752D1 DE69216752D1 (de) 1997-02-27
DE69216752T2 true DE69216752T2 (de) 1997-05-07

Family

ID=17739480

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1992616752 Expired - Fee Related DE69216752T2 (de) 1991-10-07 1992-10-02 Verfahren zur Herstellung einer Halbleiter-Scheibe

Country Status (3)

Country Link
EP (1) EP0536958B1 (de)
JP (1) JP2758093B2 (de)
DE (1) DE69216752T2 (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07247197A (ja) * 1994-03-09 1995-09-26 Fujitsu Ltd 半導体装置とその製造方法
US5629216A (en) * 1994-06-30 1997-05-13 Seh America, Inc. Method for producing semiconductor wafers with low light scattering anomalies
US5593494A (en) * 1995-03-14 1997-01-14 Memc Electronic Materials, Inc. Precision controlled precipitation of oxygen in silicon
JP4020987B2 (ja) * 1996-01-19 2007-12-12 信越半導体株式会社 ウエーハ周辺部に結晶欠陥がないシリコン単結晶およびその製造方法
US5994761A (en) 1997-02-26 1999-11-30 Memc Electronic Materials Spa Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
SG105513A1 (en) * 1997-04-09 2004-08-27 Memc Electronics Materials Inc Low defect density, ideal oxygen precipitating silicon
US6379642B1 (en) 1997-04-09 2002-04-30 Memc Electronic Materials, Inc. Vacancy dominated, defect-free silicon
EP0973964B1 (de) 1997-04-09 2002-09-04 MEMC Electronic Materials, Inc. Selbstinterstitiell dominiertes silizium mit niedriger defektdichte
DE19823962A1 (de) 1998-05-28 1999-12-02 Wacker Siltronic Halbleitermat Verfahren zur Herstellung eines Einkristalls
US6077343A (en) * 1998-06-04 2000-06-20 Shin-Etsu Handotai Co., Ltd. Silicon single crystal wafer having few defects wherein nitrogen is doped and a method for producing it
US6328795B2 (en) 1998-06-26 2001-12-11 Memc Electronic Materials, Inc. Process for growth of defect free silicon crystals of arbitrarily large diameters
US6828690B1 (en) 1998-08-05 2004-12-07 Memc Electronic Materials, Inc. Non-uniform minority carrier lifetime distributions in high performance silicon power devices
JP4405083B2 (ja) 1998-09-02 2010-01-27 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド 理想的な酸素析出シリコンウエハの製造方法
CN1181522C (zh) 1998-09-02 2004-12-22 Memc电子材料有限公司 具有改进的内部收气的热退火单晶硅片及其热处理工艺
US6336968B1 (en) 1998-09-02 2002-01-08 Memc Electronic Materials, Inc. Non-oxygen precipitating czochralski silicon wafers
CN1155074C (zh) 1998-09-02 2004-06-23 Memc电子材料有限公司 从低缺陷密度的单晶硅上制备硅-绝缘体结构
CN1296526C (zh) 1998-10-14 2007-01-24 Memc电子材料有限公司 热退火后的低缺陷密度单晶硅
US6312516B2 (en) 1998-10-14 2001-11-06 Memc Electronic Materials, Inc. Process for preparing defect free silicon crystals which allows for variability in process conditions
US6284039B1 (en) 1998-10-14 2001-09-04 Memc Electronic Materials, Inc. Epitaxial silicon wafers substantially free of grown-in defects
JP3601324B2 (ja) * 1998-11-19 2004-12-15 信越半導体株式会社 結晶欠陥の少ないシリコン単結晶ウエーハ及びその製造方法
US6284384B1 (en) 1998-12-09 2001-09-04 Memc Electronic Materials, Inc. Epitaxial silicon wafer with intrinsic gettering
US20030051656A1 (en) 1999-06-14 2003-03-20 Charles Chiun-Chieh Yang Method for the preparation of an epitaxial silicon wafer with intrinsic gettering
US6635587B1 (en) 1999-09-23 2003-10-21 Memc Electronic Materials, Inc. Method for producing czochralski silicon free of agglomerated self-interstitial defects
US6376395B2 (en) * 2000-01-11 2002-04-23 Memc Electronic Materials, Inc. Semiconductor wafer manufacturing process
US6339016B1 (en) 2000-06-30 2002-01-15 Memc Electronic Materials, Inc. Method and apparatus for forming an epitaxial silicon wafer with a denuded zone
US6599815B1 (en) 2000-06-30 2003-07-29 Memc Electronic Materials, Inc. Method and apparatus for forming a silicon wafer with a denuded zone
US7105050B2 (en) 2000-11-03 2006-09-12 Memc Electronic Materials, Inc. Method for the production of low defect density silicon
US6858307B2 (en) 2000-11-03 2005-02-22 Memc Electronic Materials, Inc. Method for the production of low defect density silicon
DE60213759T2 (de) 2001-01-26 2006-11-30 Memc Electronic Materials, Inc. Silizium mit niedriger defektdichte und mit leerstellendominiertem kern, das im wesentlichen frei von oxidationsinduzierten stapelfehlern ist
JP2004537161A (ja) 2001-04-11 2004-12-09 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド 高抵抗率ｃｚシリコンにおけるサーマルドナー生成の制御
US6955718B2 (en) 2003-07-08 2005-10-18 Memc Electronic Materials, Inc. Process for preparing a stabilized ideal oxygen precipitating silicon wafer
US7485928B2 (en) 2005-11-09 2009-02-03 Memc Electronic Materials, Inc. Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
WO2007137182A2 (en) 2006-05-19 2007-11-29 Memc Electronic Materials, Inc. Controlling agglomerated point defect and oxygen cluster formation induced by the lateral surface of a silicon single crystal during cz growth

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02263793A (ja) * 1989-04-05 1990-10-26 Nippon Steel Corp 酸化誘起積層欠陥の発生し難いシリコン単結晶及びその製造方法

Also Published As

Publication number Publication date
DE69216752D1 (de) 1997-02-27
JP2758093B2 (ja) 1998-05-25
EP0536958B1 (de) 1997-01-15
JPH05102162A (ja) 1993-04-23
EP0536958A1 (de) 1993-04-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee