KR970052023A - 에스 오 아이 소자 및 그의 제조방법 - Google Patents

에스 오 아이 소자 및 그의 제조방법 Download PDF

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Publication number
KR970052023A
KR970052023A KR1019950069461A KR19950069461A KR970052023A KR 970052023 A KR970052023 A KR 970052023A KR 1019950069461 A KR1019950069461 A KR 1019950069461A KR 19950069461 A KR19950069461 A KR 19950069461A KR 970052023 A KR970052023 A KR 970052023A
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KR
South Korea
Prior art keywords
layer
forming
soi
wafer
soi device
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KR1019950069461A
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English (en)
Inventor
김재갑
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950069461A priority Critical patent/KR970052023A/ko
Priority to TW085115674A priority patent/TW312854B/zh
Priority to DE19654280A priority patent/DE19654280B4/de
Priority to JP8357091A priority patent/JPH1074921A/ja
Priority to GB9626979A priority patent/GB2309825B/en
Priority to CN96123937A priority patent/CN1075246C/zh
Publication of KR970052023A publication Critical patent/KR970052023A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H01L29/78615—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect with a body contact

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 에스 오 아이(이하 SOI : silicon on insulator)소자 및 그의 제조방법에 관한 것으로, 특히 SOI의 기판의 플로팅(floating) 현상을 방지할 수 있는 SOI 소자 및 그의 제조방법에 관한 것으로, 본 발명에 의하면 SOI 기판의 고질적인 문제점인 기판 플로팅 현상을 방지하기 위하여 소자가 형성된 실리콘 웨이퍼 내부에 소자의 채널영역과 연결되도록 전도층을 형성하여 기판 전극 영역에 연결시키므로써, 기판의 항복 전압 및 스위칭 특성을 향상시키어 소자의 특성을 개선한다.

Description

에스 오 아이 소자 및 그의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도 (가) 내지 (다)는 본 발명에 에스 오 아이 기판 제조방법을 설명하기 위한 각 제조공정에 있어서의 요부 단면도.

Claims (4)

  1. 모스 트랜지스터를 구성하는 전극 및 소자 분리막이 형성된 SOI 소자층과, 상기 SOI 소자층 하부에 일정부분의 SOI 소자층이 노출되도록 형성된 제1절연막과, 상기 제1절연막의 하부에 위치하여 SOI 소자층에 접속되도록 형성된 전도층과, 상기 전도층 하부에 형성된 절연막과, 상기 SOI 소자를 지지하는 핸들링 웨이퍼를 포함하는 것을 특징으로 하는 SOI 소자.
  2. 실리콘 웨이퍼 상의 적소에 소자 분리막을 형성하는 단계; 상기 구조물 상부에 제1절연막을 형성하는 단계; 상기 제1절연막을 채널 예정 영역 및 기판 전극 영역에 노출되도록 식각하는 단계; 상기 구조물 상부에 전도층을 형성하는 단계; 상기 전도층 상부에 제2절연막을 형성하는 단계; 상기 제2절연막이 형성된 실리콘 웨이퍼와 부착될 핸들링 웨이퍼를 준비하는 단계; 상기 핸들링 웨이퍼 상부에 제3절연막을 형성하는 단계; 상기 핸들링 웨이퍼 및 실리콘 웨이퍼를 접착시키는 단계; 및 상기 실리콘 웨이퍼의 표면을 에치백하여 SOI층을 형성하는 단계를 포함하는 것을 특징으로 하는 SOI 소자의 제조방법.
  3. 제2항에 있어서, 상기 전도층은 기판 불순물과 동일한 타입의 불순물이 도핑된 실리콘층인 것을 특징으로 하는 SOI 소자의 제조방법.
  4. 제2항에 있어서, 상기 SOI층을 형성하기 위한 에치백 공정시, 소자 분리막을 식각 정지층으로 하여 에치백하는 것을 특징으로하는 하는 SOI 소자의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950069461A 1995-12-30 1995-12-30 에스 오 아이 소자 및 그의 제조방법 KR970052023A (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019950069461A KR970052023A (ko) 1995-12-30 1995-12-30 에스 오 아이 소자 및 그의 제조방법
TW085115674A TW312854B (ko) 1995-12-30 1996-12-19
DE19654280A DE19654280B4 (de) 1995-12-30 1996-12-24 Verfahren zur Herstellung einer Halbleitereinrichtung auf einem SOI-Wafer
JP8357091A JPH1074921A (ja) 1995-12-30 1996-12-26 半導体デバイスおよびその製造方法
GB9626979A GB2309825B (en) 1995-12-30 1996-12-27 Semiconductor device and a method of fabricating the same
CN96123937A CN1075246C (zh) 1995-12-30 1996-12-30 半导体器件及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950069461A KR970052023A (ko) 1995-12-30 1995-12-30 에스 오 아이 소자 및 그의 제조방법

Publications (1)

Publication Number Publication Date
KR970052023A true KR970052023A (ko) 1997-07-29

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Application Number Title Priority Date Filing Date
KR1019950069461A KR970052023A (ko) 1995-12-30 1995-12-30 에스 오 아이 소자 및 그의 제조방법

Country Status (6)

Country Link
JP (1) JPH1074921A (ko)
KR (1) KR970052023A (ko)
CN (1) CN1075246C (ko)
DE (1) DE19654280B4 (ko)
GB (1) GB2309825B (ko)
TW (1) TW312854B (ko)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100318463B1 (ko) * 1998-10-28 2002-02-19 박종섭 몸체접촉실리콘이중막소자제조방법

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KR100281109B1 (ko) * 1997-12-15 2001-03-02 김영환 에스오아이(soi)소자및그의제조방법
DE69925078T2 (de) 1998-08-29 2006-03-09 International Business Machines Corp. SOI-Transistor mit einem Substrat-Kontakt und Verfahren zu dessen Herstellung
EP0989613B1 (en) * 1998-08-29 2005-05-04 International Business Machines Corporation SOI transistor with body contact and method of forming same
TW476993B (en) * 2000-01-19 2002-02-21 Advanced Micro Devices Inc Silicon on insulator circuit structure with buried semiconductor interconnect structure and method for forming same
US6368903B1 (en) * 2000-03-17 2002-04-09 International Business Machines Corporation SOI low capacitance body contact
JP2003100907A (ja) 2001-09-26 2003-04-04 Mitsubishi Electric Corp 半導体記憶装置およびその製造方法
JP5567247B2 (ja) * 2006-02-07 2014-08-06 セイコーインスツル株式会社 半導体装置およびその製造方法
CN101621009B (zh) * 2008-07-02 2012-03-21 中国科学院微电子研究所 一种制作部分耗尽soi器件体接触结构的方法
JP5801300B2 (ja) 2009-07-15 2015-10-28 シランナ・セミコンダクター・ユー・エス・エイ・インコーポレイテッドＳｉｌａｎｎａ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｕ．Ｓ．Ａ．， Ｉｎｃ． 背面放熱を伴う絶縁体上半導体
TWI515878B (zh) 2009-07-15 2016-01-01 西拉娜半導體美國股份有限公司 絕緣體上半導體結構、自絕緣體上半導體主動元件之通道去除無用積聚多數型載子之方法、及製造積體電路之方法
US9496227B2 (en) 2009-07-15 2016-11-15 Qualcomm Incorporated Semiconductor-on-insulator with back side support layer
US9390974B2 (en) 2012-12-21 2016-07-12 Qualcomm Incorporated Back-to-back stacked integrated circuit assembly and method of making
CN102484097B (zh) 2009-07-15 2016-05-25 斯兰纳半导体美国股份有限公司 具有背侧支撑层的绝缘体上半导体
US9466719B2 (en) 2009-07-15 2016-10-11 Qualcomm Incorporated Semiconductor-on-insulator with back side strain topology
US8912646B2 (en) 2009-07-15 2014-12-16 Silanna Semiconductor U.S.A., Inc. Integrated circuit assembly and method of making
CN102683417A (zh) * 2012-05-17 2012-09-19 中国科学院微电子研究所 Soi mos晶体管
KR20140047494A (ko) * 2012-10-12 2014-04-22 삼성전자주식회사 서브픽셀, 이를 포함하는 이미지 센서, 및 이미지 센싱 시스템
US9215962B2 (en) 2014-03-13 2015-12-22 Ecovacs Robotics, Inc. Autonomous planar surface cleaning robot
US9515181B2 (en) 2014-08-06 2016-12-06 Qualcomm Incorporated Semiconductor device with self-aligned back side features

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US5343067A (en) * 1987-02-26 1994-08-30 Kabushiki Kaisha Toshiba High breakdown voltage semiconductor device
DE3921038C2 (de) * 1988-06-28 1998-12-10 Ricoh Kk Verfahren zur Herstellung eines Halbleitersubstrats bzw. Festkörperaufbaus
JP2547663B2 (ja) * 1990-10-03 1996-10-23 三菱電機株式会社 半導体装置
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KR100267755B1 (ko) * 1993-03-18 2000-10-16 김영환 박막트랜지스터 제조방법
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100318463B1 (ko) * 1998-10-28 2002-02-19 박종섭 몸체접촉실리콘이중막소자제조방법

Also Published As

Publication number Publication date
GB9626979D0 (en) 1997-02-12
TW312854B (ko) 1997-08-11
CN1160293A (zh) 1997-09-24
CN1075246C (zh) 2001-11-21
DE19654280B4 (de) 2005-11-10
DE19654280A1 (de) 1997-07-03
GB2309825A (en) 1997-08-06
GB2309825B (en) 2000-07-05
JPH1074921A (ja) 1998-03-17

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