TW476993B - Silicon on insulator circuit structure with buried semiconductor interconnect structure and method for forming same - Google Patents

Abstract

A silicon on insulator (SOI) substrate is formed with a base substrate, a buried oxide layer over the base substrate, and a thin silicon device layer over the buried oxide layer. A buried semiconductor interconnect structure is embedded in the buried oxide layer for providing high resistance semiconductor coupling between various devices fabricated in the silicon device layer. A method for forming an SOI substrate with a buried semiconductor interconnect structure includes forming the structure as a protrusion on the face of a first substrate and filling the non-protruding regions with an insulator to create a smooth face. The substrate is fused face down on a second substrate to form the silicon on insulator substrate.

Description

476993 A7 B7 # Printed by the Ministry of Economic Affairs I-consumer I-consumption Fi Fi. 5. Description of the invention ([Background of the Invention] [Field of the Invention] In a broad sense, the present invention is about silicon on insulator (SOI ) Circuit structure manufacturing technology, in detail, is about an SOI substrate structure with a buried semiconductor interconnect structure. [Explanation of the related technology] Traditional or bulk semiconductor transistors are embedded in a semiconductor substrate by a P-form Or N-formed conductive silicon wells. The conductive silicon is embedded in a silicon-based wafer with the opposite conductivity, and a field oxide layer is added to prevent surface inversion. The gate and source / drain diffusions are grown using common process methods. The components formed by this type are called metal oxide semiconductors (metal_

oxide-semiconductor (MOS) field effect transistors (FETs). Each FET must be electrically isolated from other FETs to avoid short circuits in the circuit. These FETs are typically interconnected via metal layers on a volume substrate to form logic circuits. Basically, these interconnect structures are based on complementary metal-oxide-semiconductor (CMOS) technology to connect P-channel and N-channel FETs to minimize energy consumption. A problem inherent in volume semiconductor logic circuits is that a large surface area is required to electrically isolate different FETs, and this isolation method is actually inappropriate for the current industry goal of reducing size. . In addition, the junction capacitance between the source / drain and the volume substrate will slow down the operation speed using such transistor components. ------- I -------- ^ (Please read the notes on the back before filling out this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 1 91693 476993 A7 B7 V. Description of the Invention (In order to solve the problem of junction capacitance and reduce the size, the technology of silicon on insulator (SOI) is becoming more and more important and popular. In the method of forming an SOI wafer, One is the use of traditional oxygen implantation technology to generate a buried insulation oxide layer under a predetermined depth under the surface of the volume wafer. The implanted oxygen will oxidize the stone oxidized into an insulating oxide. The oxide is distributed in the form of a Gaussian distribution. The center of the Gaussian distribution is at a pre-planned depth to form an insulating buried oxide layer. The second method of forming an SOI wafer is to use the first crystal A layer of insulating silicon dioxide is deposited on the round surface, and then the wafer and the second wafer are connected together by means of a hot melt process. Using SOI technology, an SOIFET includes a source region and a first semiconductor shape. The drain region is on the other side of the channel region with the opposite electrical semiconductor shape. The SOI FET is inscribed in a thin semiconductor layer along the periphery of an island-like region. The trench is used as an isolation method, and the thin semiconductor layer is S0Ia or B, which is buried on top of the buried oxide layer. Doping on the appropriate part of the island can form the desired source, drain, and conduction regions. Here Among other technologies, it can be understood that soifet will occupy a relatively small surface area on the substrate. This is because its isolation from the silicon substrate is achieved by insulating trenches and buried oxide layers, and it is equivalent to a Compared with the volume semiconductor FET, aua ^ should take it that it will also have a relatively low junction capacitance. All of these provide the ability to place larger logic circuits on a smaller area. And JM can operate its circuit at a faster clock speed. (Please read the precautions on the back before filling this page)

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91693 476993 A7 V. Description of the invention (floating body effect. This floating body effect occurs because the buried oxide layer isolates the channel or individual of the transistor from the fixed potential energy substrate, so the system is based on The recent operation of the transistor results in the storage of charge. The floating body effect will cause the current of the transistor to distort or kink in the voltage curve, which in turn causes the threshold voltage of the operating transistor to float. For channel elements such as dynamic random access memory (DRAM), the problem of floating body effects is even more significant. In such devices, the requirement for the threshold voltage to remain constant is quite strict, so The transistor will remain in the off position to avoid charge loss from the storage capacitor. Therefore, in the SOI circuit structure, it is urgent to find a method that can generate its structure. In this method, including The advantages of SOI FETs with low junction capacitance, but without the disadvantages of floating body energy. [Summary and Purpose of the Invention] ^ A primary object of the present invention is to provide a silicon-on-insulator circuit. This circuit includes a silicon-on-insulator substrate, and the substrate includes an insulating layer that separates the silicon element from the base substrate. There is a silicon element layer in the silicon element layer. The first silicon element is embedded with a silicon interconnect structure in the insulating layer. This structure is coupled to the first silicon element. This silicon interconnect structure may steal the first silicon element into the silicon element layer. The second silicon element formed. The second silicon element may be a contact point for coupling the first silicon element to other circuits, and the function of the silicon interconnect structure is to protect the first silicon element from being located on the contact point. Destruction of high esd potential. Another way is that the first silicon element can be a field effect transistor, b and the second transistor is coupled to a fixed potential, so the interconnect structure is suitable for China on this paper scale. National Standard (CNS) A4 specification (210 X 297 issued) 3 91693 476993 Ministry of Intellectual Seal A7 V. Description of the invention (4) The function is to steal the bit energy of the channel area of the field effect transistor, such as the ground wire. U 月 月 dagger A second object of the present invention is to provide a method for manufacturing a stone slab :: This method includes: ⑷ on a first substrate, =: masking out a semiconductor interconnect structure, · (_ engraving the first surface so that half = The interconnect structure is pushed up to form; (c) the top surface of the semiconductor interconnect structure pushed on the first-is covered with an insulator. The flat surface is dioxy :: surface in; = condition == film step, which may include the use of chemical vapor deposition process: is one of the coffee and T Gang, applied to the surface The opposite side of a surface is the second surface of the first substrate, which can be polished to form a silicon element layer, and the stone element structure is adjacent. ㈣ and insulators and interconnects :: The third purpose of Ming is to provide a method for manufacturing silicon on insulators. This method includes: ⑷ on the first surface of the first-Shi Xi substrate "= cover out a semiconductor interconnect Structure; (b) engraving the first surface to push the fishing interconnect structure upwards; 覆盖 covering the semiconductor interconnect structure pushed on the first surface 2 with an insulator to form a planar surface; The planar surface of the two dream substrates and the two are at least one silicon element layer and one silicon element, and the ΓΓ component layer and the insulator and the semiconductor interconnection structure are adjacent to each other. In addition, an effect field transistor can be generated in the element layer of Shixi, and the G field size of the effect field transistor is suitable for i? Ii · Home Standard (CNS) A4 specification __ Yue 4 91693 (Please read the back Note: Please fill in this page again) 476993 Printed by A7 __B7, Consumer Cooperatives, Bureau of Intellectual Property, Ministry of Economic Affairs V. Invention Description (5 / Body includes channel area, source area, and drain area. It is better that the channel area is combined to The semiconductor interconnect structure, meanwhile, the source region and the non-electrode region are electrically isolated from the semiconductor interconnect structure. The semiconductor interconnect and the structure may combine the channel region to a fixed potential, such as Ground. Another way is that the 'semiconductor interconnect structure may couple the field effect transistor to the second circuit, and protect the field effect transistor from the ESD potential on the second circuit. [Schematic of Brief Description] Figure 1 is a cross-sectional view of an embodiment according to the present invention, which shows a partially cutaway view of a circuit where silicon is located on an insulator, and Figure 2 is an embodiment according to the present invention, where Shi Xi is located on an insulator On the circuit Manufacturing method flowchart; Figure 3 (a) is a cross-sectional view of the first step of the wafer on the edge body according to the embodiment of the present invention; ^ Figure 3 (b) is a crystal on the edge body of the embodiment according to the present invention Figure 3 (c) is a cross-sectional view of the third step of the wafer on the edge body according to the embodiment of the present invention; Figure 4 (a) is a middle side view of the wafer according to the embodiment of the present invention Cross-sectional view of the fourth step of the wafer on the body; FIG. 4 (b) is a cross-sectional view of the fifth step of the wafer on the edge body according to the embodiment of the present invention; FIG. 5 (a) is an embodiment of the present invention A cross-sectional view of one of the steps for manufacturing silicon components on a middle-upper wafer. The manufacturing silicon is located at the manufacturing silicon. The manufacturing silicon is located at the manufacturing line. The manufacturing silicon is located at the manufacturing silicon. National Standard (CNS) A4 specification (210 X 297 mm) 5 91693 476993 A7 V. Description of the invention (6, 5 (b) Figure 疋 In the embodiment of the present invention, silicon is fabricated on a wafer located on an insulator Sectional view of another step of the component; [Explanation of component symbols] 10 12 14 16 (a) 18 20 22 24 26 30 3 2 34 36 38 40 41 42 44 48 54 64 16 (b) 28 46 74 66 68 70 circuit field effect transistor broken element layer element insulation trench channel region source region drain region junction surface oxide base base gate Polar oxide layer polycrystalline silicon gate interconnect structure recessed wafer mask silicon substrate N-type doped silicon oxide (oxide) (Please read the precautions on the back before filling this page) Binding --- Ministry of Economic Affairs Wisdom Printed by the Consumer Cooperative of the Property Bureau [Best Mode for Implementing the Invention] Regarding the new functions of the present invention, the description of the features of the present invention can be extended to the added patent protection scope order. However, the present invention in its preferred use state, as well as its further purposes and advantages, will refer to the detailed description of the following embodiments and the accompanying drawings to obtain the best way to understand. The reference numbers in the figure are also used to refer to the corresponding element components in.

476993 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs 5. Description of the Invention (7) Includes field effect transistor (FET) 12, and the field effect transistor system is generated in silicon layer 14 and is insulated by insulation The trench 18 is isolated from other elements 16 (a) and 16 (b) generated in the silicon element layer 14. The FET 12 includes a gate oxide layer 36 and a polysilicon gate 38. The polysilicon gate 38 is used to define a central channel region 20. The FET 12 also includes a source region 22 and a central channel region 20. The drain region 24 on the other side. In the exemplary embodiment of the present invention, the channel region 20 is preferably p-conductive silicon, and the source region 22 and the drain region 24 are both conductive silicon. Thus, two semiconductor junctions 26 and 28 are formed. However, according to known silicon technology, when the source region 22 and the drain region 24 are both conductive silicon, the channel region 20 may also be N-conductive silicon. The insulating trench 18 extends from the upper surface 30 of the SOI circuit 10 to the insulating buried oxide layer 32. The buried oxide layer 32 is located on the base substrate 4. The buried oxide layer 32 includes a buried broken interconnect structure 40, and in this exemplary embodiment, the interconnect structure is interconnected with the channel region 20 of the FET U having a silicon element 16 (a FET U. It should be possible to Cognitively, the silicon element 16 (b) can be another FET, a pipe that steals the body of the bridging 12 to the circuit (ν ^, -One can fix the FET12 channel area 20 to a fixed position to reduce the floating body effect @Positive energy drain n (sink),-Connected to the chip needle contact to isolate and protect the FET 12 from other components 16 (^ The connected body that can be affected by the upper lake position, or any other silicon device. Refer to the flowchart in Figure 2 and the structure in Figures 3, 3, and 3. Figure 8 Shi Xi with the embedded Shi Xi interconnect structure 40 is located on the insulator The crystal is produced by step 50, and the dream is produced, ^ ^ y Λ ^ is applied on the upper surface 46 of the first silicon substrate 48. The paper size is suitable for _ i ^^ Js) A4 size ⑵G χ tear public love) 7 91693 ^ -------- ^ --------- line (please read the notes on the back before filling this page) 476993 Printed cooperatives

A7 ------ g7 _V. Description of the invention (8) The cover 44 is then achieved by scoring the interconnection structure 40, as shown in Figure 3 (sentence diagram. To be more specific, 1) A layer of UV photoresist compound is added to the upper surface 46 of the first silicon substrate 48; 2) through the reticle, UV light is used to form an image pattern on the photoresist liquid; and 3) when UV light dissolves the light When the liquid is blocked, the developing solvent will harden the unexposed areas of the photoresist, and clear the photoresist in the exposed areas, leaving the unexposed areas defined by the mask 44 at the end. · In step 52, a dry residual etching method such as hydrogen bromide (Hdrogen, Hbr) is used to etch the exposed Shi Xiyu residue 'to a depth of about 500 to 1,000. Angstrom (Angstrom), thereby forming a recess 41 around the interconnection structure 40 as shown in FIG. 3 (b). Then, the photoresist cover 4 is removed and buckled in step 54. Insulating silicon dioxide 64 is deposited on the wafer, fills the recess 41, and completely covers the interconnect structure 40, and the insulating silicon dioxide 46 ' The planar result of the upper surface of is shown in Figure 3 (c). In the preferred embodiment, silicon dioxide is formed by a chemical oxygen phase deposition (CVD) process. The gas used is SIH4 or TEOS. As for the planarization method, chemical mechanical photoluminescence (chemicai) is used. mechanicai p〇Hsh, CMP). Referring to FIG. 4 (a), the second silicon substrate 66 includes a thin layer of silicon dioxide 68 having a planar upper surface 70. The first silicon substrate 48 will be flipped to the back, so the planar surface 46 will face the planar surface 70 of the second silicon substrate 66, and then the planar surface 46 'will be fused to the planar surface 70, as shown in step 4 (b). 56 shown. It should be recognized that the first silicon substrate 48 is fused to the second silicon substrate 66, and the SOI wafer 42 formed by the first silicon substrate 48 is changed to the soi by the second substrate 66. This paper standard is applicable to the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm)

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8 91693 ^ / 6993 A7 _B7 V. Description of the invention (Base substrate 34 of wafer 42. The first silicon substrate 48 will become a silicon element layer 14 'and the oxide 64 will become a buried oxide layer 32. The fusion process is usually A thermal fusion process, including heating the substrate to 10,000 to 1100. (:, to join the two substrates together. It should be recognized that the thickness of the first stone Ximei bottom 48 may be thicker than that of a silicon element The thickness of the layer 14 is expected to be thick. If this is the case, the upper surface 30 of the SOI wafer 42 may be polished to obtain the expected thickness of the silicon element layer 14. In this preferred embodiment, the expected thickness is approximately It is 1000 to 2000 angstroms, and is adjacent to the oxide layer 3 2 buried in step 58. In step 60, a silicon nitride mask 74 used to define the shape of the insulation trench 18 is formed on the upper surface 3 of the stone evening element layer 14. Is formed on the surface of the silicon element layer 14 and is aligned with the interconnect structure 40 as shown in FIG. 5 (cardiogram). One exemplary process includes generating a thin oxide layer on the upper surface 30 of the silicon element layer 14 to a thickness of about 150 to 200 Angstroms. The layer thus also creates a nitride mask 74. The mask 74 covers On the silicon element layer 14, and to protect the area to be generated by the FET 12 and the silicon element 16)), leave the area to be exposed to form the insulating trench 18. The silicon nitride mask 74 can be formed by depositing a layer of silicon nitride, Its thickness is about 15,000 to 2000 Angstroms thick, and it is located on the upper surface of the oxide layer, and then the silicon nitride is etched using traditional photolithography technology to form a circuit. In the optical lithography technology, "there is a layer Old photoresist compound is coated on the surface of silicon nitride; 2) using a UV light source and a mask to condense light to expose the photoresist and form lines; 3) when the photoresist is dissolved by the light, the developing solvent will The unexposed area of the photoresist is hardened, and the photoresist 1 in the exposed area is cleared, leaving the unexposed as defined by a nitrogen-cut surface mask. This paper size applies the CNS A4 specification (21G x 297 male). Hair) 9 91693 A7

4/6993

V. Description of the invention (U ^ heterogeneous methods are commonly known doping techniques, such as the use of ion implantation (jon lmplantati), where the ion form is n-type dopant μ, like (please read the back first (Please note this page and fill in this page again)) Arsenic 'is accelerated to a high speed in an electric field and then hits the target wafer. Because ions cannot penetrate the polysilicon gate 38, the polysilicon gate 38 can be politically Operate as a photomask, and only the exposed source and drain regions can be doped. {It should be recognized that 'manufactured SOI circuits with embedded silicon interconnects as described above' can be used in A high-resistance interconnect path is provided between the elements formed in the element layer. For example, the high-resistance interconnect path can be used to snag the channel area of a FET to a second element or other silicon element layer For example, the second component or circuit may be: υ- a circuit fixed to a fixed position to reduce the FET floating body effect; 2)-a chip connected to the chip contact to isolate the high-resistance interconnect And protect the FET from The ESD bit can affect the circuit. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Affairs, the description of the embodiments of the present invention before this paragraph is mainly for the purpose of illustration and description, and does not limit the exact form that the present invention has shown. With the above explanation, many obvious corrections or modifications in the details are possible. The selected embodiments and their descriptions are intended to provide a full explanation of the principles of the present invention, and the application examples are intended to enable people of ordinary skill in the industry to also apply the present invention and complete their understanding: Seeking different embodiments. All corrections or modifications have not deviated from the scope protected under the spirit not disclosed in this month, and these scopes will be explained below and have the fairness, justice and legal rights granted by patent protection. fgiii ^ _CNS) A4 specifications (χ Norwegian public love) 11 91693

Claims (1)

A8 B8 C8 D8 范围 Scope of patent application1. A silicon-on-insulator circuit has: X points on the insulator. The circuit contains (a) silicon on an insulator. The substrate includes a layer of insulation that separates 70 pieces of silicon from the base of the base. Layer; the third element that grows in the cutting element layer; and (c) the first element that is embedded in the insulating layer. , Xi interconnection-structure 'this insulation layer is stolen Xiang Meng is located on an insulator circuit, in which the I interconnect structure couples the first silicon element to a second silicon element formed on the layer of the stone element. For example, it is stated in the patent that the second line of Shi Xi is located on an insulator circuit, wherein the second Shi Xi component is a contact point 'for coupling a Yi Shi Xi component to other circuits' and the function of the silicon interconnect structure is to protect The first silicon element is protected from damage by high ESD potentials located at the contact points. % 4. If Shi Xi is located on the insulator circuit of the second patent application, the first Shi Xi component is a field effect transistor, and the second component is stolen to a fixed consumer intellectual cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Printed energy. Therefore, the function of the interconnect structure is to combine the potential energy of the channel region of the field effect transistor with a fixed potential energy. 5. If Shi Xi is located on the insulator circuit, the fixed position can be the ground wire. 6. A method for manufacturing a wafer on an insulator, the method comprising: 光 masking a semiconductor interconnect structure on a first surface of a first silicon substrate; (b) engraving a first surface to enable semiconductors The interconnection structure is pushed up. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love). 91693 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. A8 B8 C8 D8. 6. The scope of patent application is formed; (C) Covering the first surface of Chu Zhi with a insulator, forming a planar surface on the semiconductor interconnect structure pushed upward; and (d) inserting the planar surface into the planar surface of the first silicon substrate Two degrees 7. If the method for manufacturing wafers on insulators that are specifically designed for item 6 is applied, it will impact the planar surface of the second broken substrate. 8. The method for manufacturing a wafer with Shi Xi on insulators as claimed in item 7 of the patent application 'wherein the step of covering the thin film on the surface of Shi Xi with a method including chemical vapor deposition process will be at least SIH4 and TE. A process of applying s to the first silicon surface. 9. If the method for manufacturing a wafer on an insulator as described in item 8 of the patent application scope is further improved, it includes polishing the second surface of the first substrate on the other side of the first surface to form a broken element layer, and The broken element layer is adjacent to the insulator and the interconnect structure. 10. A method of manufacturing a circuit on which silicon is on an insulator, the method comprising: (a) photomasking a semiconductor interconnect structure on a first surface of a first silicon substrate; (b) etching the first surface to allow semiconductors to interact with each other The connection structure is pushed upward to form; (c) the first surface is covered with an insulator to form a planar surface on the semiconductor interconnect structure pushed upward; (d) the planar surface is fused to a planar surface of the second silicon substrate ; And ------------- installed -------- order · -------- line (please read the precautions on the back before filling this page) The standard is applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm) 13 91693 476993 ts8 ____ §__ VI. Patent application scope (e) At least one silicon element layer and one silicon are manufactured in the first substrate And the silicon element layer is adjacent to the insulator and the interconnect structure. 11. The method for manufacturing a silicon-on-insulator circuit according to item 10 of the scope of patent application, further comprising generating an effect field transistor in the silicon element layer, the effect field transistor including a channel region, a source region, and a drain region, The channel region is coupled to the semiconductor interconnect structure. 12. The method for manufacturing a silicon-on-insulator circuit according to item n of the patent application, wherein the source region and the non-electrode region are electrically isolated from the semiconductor interconnect structure. 13. The method for manufacturing a silicon-on-insulator circuit according to item 12 of the patent application, wherein the semiconductor interconnect structure couples the channel region to a fixed potential energy. 14. The method for manufacturing a silicon-on-insulator circuit according to item 13 of the patent application, wherein the fixed bit energy is a ground wire. 1 5 · As stated in item 11 of the patent scope, a method for manufacturing a circuit on a insulator 'where the semiconductor interconnect structure incorporates a field effect transistor to a second circuit' and guarantees that the field effect transistor is not subject to Influence of Esd bit energy on the second circuit. (Please read the notes on the back before filling this page) -III IIII.i IIII Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with China National Standard (CNS) A4 (21〇χ 297 mm) 14 91693