WO2001054174A1 - Silicon on insulator circuit structure with buried semiconductor interconnect structure and method for forming same - Google Patents

Silicon on insulator circuit structure with buried semiconductor interconnect structure and method for forming same Download PDF

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Publication number
WO2001054174A1
WO2001054174A1 PCT/US2000/034212 US0034212W WO0154174A1 WO 2001054174 A1 WO2001054174 A1 WO 2001054174A1 US 0034212 W US0034212 W US 0034212W WO 0154174 A1 WO0154174 A1 WO 0154174A1
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WIPO (PCT)
Prior art keywords
silicon
insulator
interconnect structure
substrate
circuit
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PCT/US2000/034212
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French (fr)
Inventor
Matthew S. Buynoski
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Advanced Micro Devices, Inc.
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Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO2001054174A1 publication Critical patent/WO2001054174A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps

Definitions

  • the present invention relates generally to silicon on insulator (SOI) circuit structure fabrication techniques, and more specifically to an SOI substrate structure with a buried semiconductor interconnect structure.
  • SOI silicon on insulator
  • MOS metal-oxide- semiconductor
  • FETs field effect transistors
  • MOS metal-oxide- semiconductor
  • Each of these FETs must be electrically isolated from the others in order to avoid shorting the circuits.
  • FETs are typically interconnected through metal layers above the bulk substrate to form logic circuits. Typically, the interconnections will be structured to interconnect both P-Channel and N-Channel FET's in accordance with known complimentary metal oxide semiconductor (CMOS) techniques to minimize power consumption.
  • CMOS complimentary metal oxide semiconductor
  • a problem with bulk semiconductor logic circuits is that a relatively large amount of surface area is needed for the electrical isolation of the various FETs which is undesirable for the current industry goals for size reduction. Additionally, junction capacitance between the source/drain and the bulk substrate slows the speed at which a device using such transistors can operate.
  • SOI silicon on insulator technology
  • One method of forming an SOI wafer includes using conventional oxygen implantation techniques to create an insulating buried oxide layer at a predetermined depth below the surface of a bulk wafer. The implanted oxygen oxidizes the silicon into insulating silicon dioxide in a guassian distribution pattern centered at the predetermined depth to form the insulating buried oxide layer.
  • a second method of forming an SOI wafer includes depositing an insulating layer of silicon dioxide on the surface of a first wafer and then bonding such wafer to a second wafer using a heat fusion process.
  • an SOI FET includes a source region and drain region of a first semiconductor type on opposing sides of a channel region of the opposite semiconductor type.
  • An SOI FET is isolated by etching a trench around the periphery of an island in the thin semiconductor layer above the insulating buried oxide layer in the SOI wafer. Appropriate portions of the island are doped to form the source region, drain region, and channel region. It is recognized in the art that an SOI FET will occupy less surface area on the substrate and, because it is isolated from the silicon substrate by the insulating trench and the insulating buried oxide layer, will have a lower junction capacitance than an equivalent bulk semiconductor FET. This provides for the ability to put larger logic circuits in less space and operate such circuits at faster clock speeds.
  • the floating body effect occurs because the buried oxide layer isolates the channel, or body, of the transistor from the fixed potential silicon substrate and therefore the body takes on charge based on recent operation of the transistor.
  • the floating body effect causes the current-to-voltage curve for the transistor to distort or kink, which in turn causes the threshold voltage for operating the transistor to fluctuate.
  • DRAM dynamic random access memory
  • a first objective of this invention is to provide a silicon on insulator circuit comprising a silicon on insulator substrate including an insulating layer separating a silicon device layer from a base substrate.
  • a first silicon device is fabricated in the silicon device layer and a silicon interconnect structure is embedded in the insulating layer and coupled to the first silicon device.
  • the silicon interconnect structure may couple the first silicon device to a second silicon device formed in the silicon device layer.
  • the second silicon device may be a contact for couphng the first silicon device to another circuit, the silicon interconnect structure functioning to protect the first silicon device from a high ESD potential at the contact.
  • the first device may be a field effect transistor and the second device is coupled to a fixed potential such that the interconnect structure functions to couple the potential of a channel region of the field effect transistor to a fixed potential, such as ground.
  • a second object of this invention is to provide method of fabricating a silicon on insulator wafer including: (a) masking a semiconductor interconnect structure on a first surface of a first silicon substrate; (b) etching the first surface such that a semiconductor interconnect structure protrudes therefrom; (c) coating the first surface with an insulator and forming a planar surface above the protruding semiconductor interconnect structure; and (d) fusing the planar surface to a planar surface of a second silicon substrate.
  • the planar surface of the second silicon substrate is silicon dioxide.
  • the step of coating the first surface may include applying at least one of SIH4 and TEOS to the first surface using a chemical vapor deposition process.
  • a second surface, on the opposing side of the first surface, of the first substrate may be polished to form a silicon device layer adjacent to the insulator and the interconnect structure.
  • a third objective of this invention is to provide a method of fabricating a silicon on insulator circuit, including: (a) masking a semiconductor interconnect structure on a first surface of a first silicon substrate; (b) etching the first surface such that a semiconductor interconnect structure protrudes therefrom; (c) coating the first surface with an insulator and forming a planar surface above the protruding semiconductor interconnect structure; (d) fusing the planar surface to a planar surface of a second silicon substrate; and (e) fabricating at least one silicon device a silicon device layer in the first substrate, the silicon device layer being adjacent to the insulator and the semiconductor interconnect structure.
  • a effect transistor including a channel region, source region, and drain region may be fabricated in the silicon device layer.
  • the channel region couples to the semiconductor interconnect structure while the source region and drain region are electrically isolated form the semiconductor interconnect structure.
  • the semiconductor interconnect structure may couple the channel region to a fixed potential such as ground.
  • the semiconductor interconnect structure may couple the field effect transistor to second circuit and protects the field effect transistor from ESD potential at the second circuit.
  • Figure 1 is a is a perspective view, partially cut away, of a silicon on insulator circuit in accordance with one embodiment of this invention.
  • Figure 2 is a flow chart of a method of fabricating a silicon on insulator circuit in accordance with one embodiment of this invention.
  • Figure 3(a) is a cross sectional view of a first step in the fabrication of a silicon on insulator wafer in accordance with one embodiment of this invention.
  • Figure 3(b) is a cross sectional view of a second step in the fabrication of a silicon on insulator wafer in accordance with one embodiment of this invention.
  • Figure 3(c) is a cross sectional view of a third step in the fabrication of a silicon on insulator wafer in accordance with one embodiment of this invention.
  • Figure 4(a) is a cross sectional view of a fourth step in the fabrication of a silicon on insulator wafer in accordance with one embodiment of this invention.
  • Figure 4(b) is a cross sectional view of a fifth step in the fabrication of a silicon on insulator wafer in accordance with one embodiment of this invention.
  • Figure 5(a) is a cross sectional view of a step in the fabrication of silicon devices on a silicon on insulator wafer in accordance with one embodiment of this invention.
  • Figure 5(b) is a cross sectional view of another step in the fabrication of silicon devices on a silicon on insulator wafer in accordance with one embodiment of this invention.
  • silicon on insulator (SOI) circuit 10 of this invention includes field effect transistor (FET) 12 formed in a silicon device layer 14 and isolated from other devices 16(a) and 16(b) formed in the silicon device layer 14 by an insulating trench 18.
  • the FET 12 includes a gate oxide layer 36 and a polysilicon gate 38 which defines a central channel region 20, and a source region 22 and a drain region 24 on opposing sides of the central channel region 20.
  • the channel region 20 is preferably P-conductivity silicon while the source region 22 and the drain region 24 are each N-conductivity silicon to form two semiconductor junctions 26 and 28.
  • the channel region 20 may be N-conductivity silicon while each of the source region 22 and the drain region 24 are P-conductivity silicon.
  • the insulating trench 18 extends from the top face 30 of the SOI circuit 10 to an insulating buried oxide layer 32.
  • the buried oxide layer 32 is on top of a base substrate 34.
  • the buried oxide layer 32 includes a buried silicon interconnect structure 40 which, in the exemplary embodiment, interconnects the channel region 20 of FET 12 with silicon device 16(b).
  • silicon device 16(b) may be another FET, a via for coupling the body of FET 12 to another circuit formed in metal layers (not shown) above the SOI circuit 10, a fixed potential sink for tying the potential of the FET 12 channel region 20 to a fixed potential for reducing the floating body effect, an interconnect to a chip pin contact to isolate and protect the FET 12 from and ESD potential on the other device 16(b), or any other silicon device.
  • a silicon- on-insulator wafer with a buried silicon interconnect structure 40 is formed by applying a mask 44 to define and mask interconnect structure 40 on the top face 46 of a first silicon substrate 48 in step 50 and as shown in Figure 3(a).
  • a layer of a UV sensitive photoresist compound is applied to the top face 46 of the first silicon substrate 48; 2) UV light is used to image a pattern from a reticle onto the photoresist; and 3) A developer solution hardens the unexposed areas of the photoresist while the UV light dissolves the photoresist and the developer washes away the photoresist in the exposed portions thereby leaving the unexposed portions as the mask 44.
  • step 52 a dry etch with an etching compound such as hydrogen bromide (Hbr) that etches away the exposed silicon to a depth of approximately 500 - 1,000 Angstroms to form a recess 41 around the perimeter of interconnect structure 40 protruding therefrom as shown in Figure 3(b). Thereafter, photoresist mask 44 is removed.
  • an etching compound such as hydrogen bromide (Hbr) that etches away the exposed silicon to a depth of approximately 500 - 1,000 Angstroms to form a recess 41 around the perimeter of interconnect structure 40 protruding therefrom as shown in Figure 3(b).
  • insulating silicon dioxide 64 is deposited on the wafer to fill the recess 41 and to completely cover the interconnect structure 40 and the top surface of the insulating silicon dioxide 46' is planarized as shown in Figure 3(c).
  • the silicon dioxide is deposited using a chemical vapor deposition (CVD) process with a gas such as SIH4 or TEOS and is planarized using a chemical mechanical polish (CMP).
  • CVD chemical vapor deposition
  • CMP chemical mechanical polish
  • a second silicon substrate 66 includes a thin layer of silicon dioxide 68 with a planar top face 70.
  • the first silicon substrate 48 is turned upside down such that planar face 46' faces planar face 70 of the second silicon substrate 66 and planar face 46' is then fused to planar face 70 as shown in Figure 4(b) at step 56.
  • fusing the first substrate 48 to second substrate 66 forms SOI wafer 42 with the second substrate 66 becoming the base substrate 34 of SOI wafer 42.
  • the first substrate 48 becomes the silicon device layer 14 and the oxide 64 becomes the buried oxide layer 32.
  • the fusing process is typically a heat fusion process which includes heating the substrates to 1,000 - 1,100C to bond the two substrates.
  • the thickness of the first substrate 48 may be thicker than the desired thickness of silicon device layer 14, and as such, the top face 30 of the SOI wafer 42 may have to be polished to obtain the desired thickness of silicon device layer 14, which in the preferred embodiment is approximately 1 ,000 - 2,000 Angstroms adjacent to the buried oxide layer 32 at step 58.
  • silicon nitride mask 74 which defines insulating trenches 18 is formed on the top surface 30 of the silicon device layer 14 in alignment with the interconnect circuit structure 40 as shown in Figure 5(a).
  • One exemplary process includes forming a thin layer of oxide approximately 150-200 Angstroms thick (not shown) is formed on the top surface 30 of the silicon device layer 14 and a silicon nitride mask 74 is formed thereon.
  • the mask 74 covers and protects the silicon device layer 14 in the area where the FET 12 and silicon device 16(b) are to be formed while leaving the area where the insulating trench 18 is to be formed exposed.
  • the sihcon nitride mask 74 may be formed by depositing a layer of silicon nitride, approximate 1 ,500-2,000 Angstroms thick, on the top surface of the oxide and patterning and etching the silicon nitride using conventional photolithography techniques wherein 1) a layer of a UV sensitive photoresist compound is applied to the surface of the silicon nitride; 2) a UV light source and a reticle provide collimated illumination used to expose and pattern the photoresist; 3) A developer solution hardens the unexposed areas of the photoresist while the UV light dissolves the photoresist and the developer washes it away in the exposed portions thereby leaving the unexposed portions as a mask on the surface of the silicon nitride; and 4) a dry etch with an etching compound that etches silicon nitride while not etching the photoresist removes the silicon nitride layer in the areas that are not masked with the photoresist thereby creating
  • the etching chemistry is changed as appropriate to etch insulating trench 18 through the silicon device layer 14 and into the buried oxide layer 32.
  • the insulating trench 18 is then filled with insulating silicon dioxide using a chemical vapor deposition process with a gas such as SIH4 or TEOS as is known in the art.
  • a chemical mechanical polish is then used to remove the remaining silicon nitride mask 74.
  • FET 12 is formed by forming the gate oxide layer 36, and the polysilicon gate 38 on the top surface 30 of the silicon device layer 14 to define the channel region 20 in a conventional CMOS self aligned gate, source, and drain process as shown in Figure 5(b).
  • the gate oxide layer 36 is typically grown on the surface of the silicon device layer 14 using a thermal oxidization process and a polysilicon layer is deposited on top of the gate oxide layer 36 using a low pressure chemical vapor deposition (LPCVD) process.
  • LPCVD low pressure chemical vapor deposition
  • the polysilicon layer is then patterned and etched using the photolithography method discussed earlier to create polysilicon gate 38 which defines the channel region 20 of the FET 12.
  • the portions of FET 12 on opposing sides of the P-type silicon in the channel region 20 that are not masked by the gate 38 applied in step 60 are doped into N-type silicon using known doping processes such as ion implantation wherein ions of an N-type dopant 54, such as arsenic are accelerated to a high velocity in an electric field and impinge on the target wafer. Because the ions cannot penetrate the polysilicon gate 38, the polysilicon gate 38 effectively operates as a mask which results in doping only the exposed source region and drain region.
  • the foregoing processes of fabricating an SOI circuit with a buried sihcon interconnect structure provides for a high resistance interconnect path between devices formed in the silicon device layer.
  • the high resistance interconnect path can be used to couple the channel region of a FET to a second device or circuit formed in the silicon device layer.
  • the second device or circuit could be, for example: 1 ) a circuit to a fixed potential sink to reduce the floating body effects of the FET; or 2) a circuit to chip contact susceptible to ESD such that the high resistance interconnect path protects the FET from ESD damage.

Abstract

A silicon on insulator (SOI) substrate is formed with a base substrate, a buried oxide layer over the base substrate, and a thin silicon device layer over the buried oxide layer. A buried semiconductor interconnect structure is embedded in the buried oxide layer for providing high resistance semiconductor coupling between various devices fabricated in the silicon device layer. A method for forming an SOI substrate with a buried semiconductor interconnect structure includes forming the structure as a protrusion on the face of a first substrate and filling the non-protruding regions with an insulator to create a smooth face. The substrate is fused face down on a second substrate to form the silicon on insulator substrate.

Description

SILICON ON INSULATOR CIRCUIT STRUCTURE WITH BURIED
SEMICONDUCTOR INTERCONNECT STRUCTURE AND
METHOD FOR FORMING SAME
TECHNICAL FTFliP
The present invention relates generally to silicon on insulator (SOI) circuit structure fabrication techniques, and more specifically to an SOI substrate structure with a buried semiconductor interconnect structure. RAΓKOROTTND ART
Conventional or bulk semiconductor transistors are formed in a semiconductor substrate by implanting a well of either P-type or N-type conductivity silicon in a silicon substrate wafer of the opposite conductivity, plus a field oxide to prevent surface inversion. Gates and source/drain diffusions are then manufactured using commonly known processes. These form devices known as metal-oxide- semiconductor (MOS) field effect transistors (FETs). Each of these FETs must be electrically isolated from the others in order to avoid shorting the circuits. These FETs are typically interconnected through metal layers above the bulk substrate to form logic circuits. Typically, the interconnections will be structured to interconnect both P-Channel and N-Channel FET's in accordance with known complimentary metal oxide semiconductor (CMOS) techniques to minimize power consumption.
A problem with bulk semiconductor logic circuits is that a relatively large amount of surface area is needed for the electrical isolation of the various FETs which is undesirable for the current industry goals for size reduction. Additionally, junction capacitance between the source/drain and the bulk substrate slows the speed at which a device using such transistors can operate.
In order to deal with the junction capacitance problem and reduce size, silicon on insulator technology (SOI) has been gaining popularity. One method of forming an SOI wafer includes using conventional oxygen implantation techniques to create an insulating buried oxide layer at a predetermined depth below the surface of a bulk wafer. The implanted oxygen oxidizes the silicon into insulating silicon dioxide in a guassian distribution pattern centered at the predetermined depth to form the insulating buried oxide layer. A second method of forming an SOI wafer includes depositing an insulating layer of silicon dioxide on the surface of a first wafer and then bonding such wafer to a second wafer using a heat fusion process.
Utilizing SOI technology, an SOI FET includes a source region and drain region of a first semiconductor type on opposing sides of a channel region of the opposite semiconductor type. An SOI FET is isolated by etching a trench around the periphery of an island in the thin semiconductor layer above the insulating buried oxide layer in the SOI wafer. Appropriate portions of the island are doped to form the source region, drain region, and channel region. It is recognized in the art that an SOI FET will occupy less surface area on the substrate and, because it is isolated from the silicon substrate by the insulating trench and the insulating buried oxide layer, will have a lower junction capacitance than an equivalent bulk semiconductor FET. This provides for the ability to put larger logic circuits in less space and operate such circuits at faster clock speeds.
One problem with forming field effect transistors on an SOI wafer is the floating body effect. The floating body effect occurs because the buried oxide layer isolates the channel, or body, of the transistor from the fixed potential silicon substrate and therefore the body takes on charge based on recent operation of the transistor. The floating body effect causes the current-to-voltage curve for the transistor to distort or kink, which in turn causes the threshold voltage for operating the transistor to fluctuate. This problem is particularly apparent for passgate devices used in such devices as dynamic random access memory (DRAM) wherein it is critical that the threshold voltage remain fixed such that the transistor remains in the "Off position to prevent charge leakage from the storage capacitor.
Accordingly, there is a strong need in the art for an SOI circuit structure, and a method for forming such structure, that includes the low junction capacitance characteristics of the SOI FET but does not suffer the disadvantage of a floating body potential. nisπ OSTTRF OF THF INVENTION
A first objective of this invention is to provide a silicon on insulator circuit comprising a silicon on insulator substrate including an insulating layer separating a silicon device layer from a base substrate. A first silicon device is fabricated in the silicon device layer and a silicon interconnect structure is embedded in the insulating layer and coupled to the first silicon device. The silicon interconnect structure may couple the first silicon device to a second silicon device formed in the silicon device layer. The second silicon device may be a contact for couphng the first silicon device to another circuit, the silicon interconnect structure functioning to protect the first silicon device from a high ESD potential at the contact. Alternatively, the first device may be a field effect transistor and the second device is coupled to a fixed potential such that the interconnect structure functions to couple the potential of a channel region of the field effect transistor to a fixed potential, such as ground.
A second object of this invention is to provide method of fabricating a silicon on insulator wafer including: (a) masking a semiconductor interconnect structure on a first surface of a first silicon substrate; (b) etching the first surface such that a semiconductor interconnect structure protrudes therefrom; (c) coating the first surface with an insulator and forming a planar surface above the protruding semiconductor interconnect structure; and (d) fusing the planar surface to a planar surface of a second silicon substrate. Preferably, the planar surface of the second silicon substrate is silicon dioxide. The step of coating the first surface may include applying at least one of SIH4 and TEOS to the first surface using a chemical vapor deposition process.
A second surface, on the opposing side of the first surface, of the first substrate may be polished to form a silicon device layer adjacent to the insulator and the interconnect structure. A third objective of this invention is to provide a method of fabricating a silicon on insulator circuit, including: (a) masking a semiconductor interconnect structure on a first surface of a first silicon substrate; (b) etching the first surface such that a semiconductor interconnect structure protrudes therefrom; (c) coating the first surface with an insulator and forming a planar surface above the protruding semiconductor interconnect structure; (d) fusing the planar surface to a planar surface of a second silicon substrate; and (e) fabricating at least one silicon device a silicon device layer in the first substrate, the silicon device layer being adjacent to the insulator and the semiconductor interconnect structure. Further, a effect transistor including a channel region, source region, and drain region may be fabricated in the silicon device layer. Preferably, the channel region couples to the semiconductor interconnect structure while the source region and drain region are electrically isolated form the semiconductor interconnect structure. The semiconductor interconnect structure may couple the channel region to a fixed potential such as ground. Alternatively, the semiconductor interconnect structure may couple the field effect transistor to second circuit and protects the field effect transistor from ESD potential at the second circuit. BRTFF DESCRIPTION OF THF DRAWINGS
Figure 1 is a is a perspective view, partially cut away, of a silicon on insulator circuit in accordance with one embodiment of this invention.
Figure 2 is a flow chart of a method of fabricating a silicon on insulator circuit in accordance with one embodiment of this invention.
Figure 3(a) is a cross sectional view of a first step in the fabrication of a silicon on insulator wafer in accordance with one embodiment of this invention.
Figure 3(b) is a cross sectional view of a second step in the fabrication of a silicon on insulator wafer in accordance with one embodiment of this invention.
Figure 3(c) is a cross sectional view of a third step in the fabrication of a silicon on insulator wafer in accordance with one embodiment of this invention.
Figure 4(a) is a cross sectional view of a fourth step in the fabrication of a silicon on insulator wafer in accordance with one embodiment of this invention.
Figure 4(b) is a cross sectional view of a fifth step in the fabrication of a silicon on insulator wafer in accordance with one embodiment of this invention.
Figure 5(a) is a cross sectional view of a step in the fabrication of silicon devices on a silicon on insulator wafer in accordance with one embodiment of this invention.
Figure 5(b) is a cross sectional view of another step in the fabrication of silicon devices on a silicon on insulator wafer in accordance with one embodiment of this invention. MODFS FOR TARRYING OTTT THE INVENTION
The present invention will now be described in detail with reference to the drawings. In the drawings, like reference numerals are used to refer to like elements throughout.
Referring to Figure 1, silicon on insulator (SOI) circuit 10 of this invention includes field effect transistor (FET) 12 formed in a silicon device layer 14 and isolated from other devices 16(a) and 16(b) formed in the silicon device layer 14 by an insulating trench 18. The FET 12 includes a gate oxide layer 36 and a polysilicon gate 38 which defines a central channel region 20, and a source region 22 and a drain region 24 on opposing sides of the central channel region 20. In the exemplary embodiment of this invention, the channel region 20 is preferably P-conductivity silicon while the source region 22 and the drain region 24 are each N-conductivity silicon to form two semiconductor junctions 26 and 28. However, in accordance with known silicon technology, the channel region 20 may be N-conductivity silicon while each of the source region 22 and the drain region 24 are P-conductivity silicon. The insulating trench 18 extends from the top face 30 of the SOI circuit 10 to an insulating buried oxide layer 32. The buried oxide layer 32 is on top of a base substrate 34. The buried oxide layer 32 includes a buried silicon interconnect structure 40 which, in the exemplary embodiment, interconnects the channel region 20 of FET 12 with silicon device 16(b). It should be appreciated that silicon device 16(b) may be another FET, a via for coupling the body of FET 12 to another circuit formed in metal layers (not shown) above the SOI circuit 10, a fixed potential sink for tying the potential of the FET 12 channel region 20 to a fixed potential for reducing the floating body effect, an interconnect to a chip pin contact to isolate and protect the FET 12 from and ESD potential on the other device 16(b), or any other silicon device.
Referring to the flowchart of Figure 2 and the diagrams of Figures 3(a), 3(b), and 3(c), a silicon- on-insulator wafer with a buried silicon interconnect structure 40 is formed by applying a mask 44 to define and mask interconnect structure 40 on the top face 46 of a first silicon substrate 48 in step 50 and as shown in Figure 3(a). More specifically, a layer of a UV sensitive photoresist compound is applied to the top face 46 of the first silicon substrate 48; 2) UV light is used to image a pattern from a reticle onto the photoresist; and 3) A developer solution hardens the unexposed areas of the photoresist while the UV light dissolves the photoresist and the developer washes away the photoresist in the exposed portions thereby leaving the unexposed portions as the mask 44.
In step 52, a dry etch with an etching compound such as hydrogen bromide (Hbr) that etches away the exposed silicon to a depth of approximately 500 - 1,000 Angstroms to form a recess 41 around the perimeter of interconnect structure 40 protruding therefrom as shown in Figure 3(b). Thereafter, photoresist mask 44 is removed.
In step 54 insulating silicon dioxide 64 is deposited on the wafer to fill the recess 41 and to completely cover the interconnect structure 40 and the top surface of the insulating silicon dioxide 46' is planarized as shown in Figure 3(c). In the preferred embodiment, the silicon dioxide is deposited using a chemical vapor deposition (CVD) process with a gas such as SIH4 or TEOS and is planarized using a chemical mechanical polish (CMP). Referring to Figure 4(a), a second silicon substrate 66 includes a thin layer of silicon dioxide 68 with a planar top face 70. The first silicon substrate 48 is turned upside down such that planar face 46' faces planar face 70 of the second silicon substrate 66 and planar face 46' is then fused to planar face 70 as shown in Figure 4(b) at step 56. It should be appreciated that fusing the first substrate 48 to second substrate 66 forms SOI wafer 42 with the second substrate 66 becoming the base substrate 34 of SOI wafer 42. The first substrate 48 becomes the silicon device layer 14 and the oxide 64 becomes the buried oxide layer 32. The fusing process is typically a heat fusion process which includes heating the substrates to 1,000 - 1,100C to bond the two substrates. It should be appreciated that the thickness of the first substrate 48 may be thicker than the desired thickness of silicon device layer 14, and as such, the top face 30 of the SOI wafer 42 may have to be polished to obtain the desired thickness of silicon device layer 14, which in the preferred embodiment is approximately 1 ,000 - 2,000 Angstroms adjacent to the buried oxide layer 32 at step 58.
At step 60, silicon nitride mask 74 which defines insulating trenches 18 is formed on the top surface 30 of the silicon device layer 14 in alignment with the interconnect circuit structure 40 as shown in Figure 5(a). One exemplary process includes forming a thin layer of oxide approximately 150-200 Angstroms thick (not shown) is formed on the top surface 30 of the silicon device layer 14 and a silicon nitride mask 74 is formed thereon. The mask 74 covers and protects the silicon device layer 14 in the area where the FET 12 and silicon device 16(b) are to be formed while leaving the area where the insulating trench 18 is to be formed exposed. The sihcon nitride mask 74 may be formed by depositing a layer of silicon nitride, approximate 1 ,500-2,000 Angstroms thick, on the top surface of the oxide and patterning and etching the silicon nitride using conventional photolithography techniques wherein 1) a layer of a UV sensitive photoresist compound is applied to the surface of the silicon nitride; 2) a UV light source and a reticle provide collimated illumination used to expose and pattern the photoresist; 3) A developer solution hardens the unexposed areas of the photoresist while the UV light dissolves the photoresist and the developer washes it away in the exposed portions thereby leaving the unexposed portions as a mask on the surface of the silicon nitride; and 4) a dry etch with an etching compound that etches silicon nitride while not etching the photoresist removes the silicon nitride layer in the areas that are not masked with the photoresist thereby creating the silicon nitride mask below the photoresist mask.
Thereafter, at step 62, the etching chemistry is changed as appropriate to etch insulating trench 18 through the silicon device layer 14 and into the buried oxide layer 32. The insulating trench 18 is then filled with insulating silicon dioxide using a chemical vapor deposition process with a gas such as SIH4 or TEOS as is known in the art. A chemical mechanical polish is then used to remove the remaining silicon nitride mask 74.
At step 63, FET 12 is formed by forming the gate oxide layer 36, and the polysilicon gate 38 on the top surface 30 of the silicon device layer 14 to define the channel region 20 in a conventional CMOS self aligned gate, source, and drain process as shown in Figure 5(b). The gate oxide layer 36 is typically grown on the surface of the silicon device layer 14 using a thermal oxidization process and a polysilicon layer is deposited on top of the gate oxide layer 36 using a low pressure chemical vapor deposition (LPCVD) process. The polysilicon layer is then patterned and etched using the photolithography method discussed earlier to create polysilicon gate 38 which defines the channel region 20 of the FET 12.
The portions of FET 12 on opposing sides of the P-type silicon in the channel region 20 that are not masked by the gate 38 applied in step 60 are doped into N-type silicon using known doping processes such as ion implantation wherein ions of an N-type dopant 54, such as arsenic are accelerated to a high velocity in an electric field and impinge on the target wafer. Because the ions cannot penetrate the polysilicon gate 38, the polysilicon gate 38 effectively operates as a mask which results in doping only the exposed source region and drain region.
It should be appreciated that the foregoing processes of fabricating an SOI circuit with a buried sihcon interconnect structure provides for a high resistance interconnect path between devices formed in the silicon device layer. For example, the high resistance interconnect path can be used to couple the channel region of a FET to a second device or circuit formed in the silicon device layer. The second device or circuit could be, for example: 1 ) a circuit to a fixed potential sink to reduce the floating body effects of the FET; or 2) a circuit to chip contact susceptible to ESD such that the high resistance interconnect path protects the FET from ESD damage.
Although the invention has been shown and described with respect to certain preferred embodiments, it is obvious that equivalents and modifications will occur to others skilled in the art upon the reading and understanding of the specification. The present invention includes all such equivalents and modifications, and is limited only by the scope of the following claims.

Claims

GT ATMSWhat is claimed is:
1. A silicon on insulator circuit comprising: a) a silicon on insulator substrate including an insulating layer separating a silicon device layer from a base substrate; b) a first silicon device fabricated in the silicon device layer; and c) a silicon interconnect structure embedded in the insulating layer coupled to the first silicon device.
2. The silicon on insulator circuit of claim 1, wherein the silicon interconnect structure couples the first silicon device to a second silicon device formed in the silicon device layer.
3. The silicon on insulator circuit of claim 2, wherein the second silicon device is a contact for coupling the first silicon device to another circuit, the silicon interconnect structure functioning to protect the first silicon device from a high ESD potential at the contact.
4. The silicon on insulator circuit of claim 2, wherein the first device is a field effect transistor and the second device is coupled to a fixed potential such that the interconnect structure functions to couples the potential of a channel region of the field effect transistor to a fixed potential.
5. The sihcon on insulator circuit of claim 4, wherein the fixed potential is ground.
6. A method of fabricating a silicon on insulator wafer, comprising:
(a) masking a semiconductor interconnect structure on a first surface of a first silicon substrate;
(b) etching the first surface such that a semiconductor interconnect structure protrudes therefrom;
(c) coating the first surface with an insulator and forming a planar surface above the protruding semiconductor interconnect structure; and
(d) fusing the planar surface to a planar surface of a second silicon substrate.
7. The method of fabricating a silicon on insulator wafer of claim 6, wherein the planar surface of the second silicon substrate is silicon dioxide.
8. The method of fabricating a silicon on insulator wafer of claim 7, wherein the step of coating the first surface includes applying at least one of SIH4 and TEOS to the first surface using a chemical vapor deposition process.
9. The method of fabricating a silicon on insulator wafer of claim 8, further including polishing a second surface of the first substrate, the second surface being on the opposing side of the first surface, to form a silicon device layer adjacent to the insulator and the interconnect structure.
10. A method of fabricating a sihcon on insulator circuit, comprising:
(a) masking a semiconductor interconnect structure on a first surface of a first silicon substrate;
(b) etching the first surface such that a semiconductor interconnect structure protrudes therefrom;
(c) coating the first surface with an insulator and forming a planar surface above the protruding semiconductor interconnect structure;
(d) fusing the planar surface to a planar surface of a second silicon substrate; and
(e) fabricating at least one silicon device a silicon device layer in the first substrate, the silicon device layer being adjacent to the insulator and the semiconductor interconnect structure.
11. The method of fabricating the sihcon on insulator circuit of claim 10, further including fabricating a field effect transistor including a channel region, source region, and drain region in the sihcon device layer, the channel region coupling to the semiconductor interconnect structure.
12. The method of fabricating the silicon on insulator circuit of claim 11, wherein the source region and drain region are electrically isolated form the semiconductor interconnect structure.
13. The method of fabricating the silicon on insulator circuit of claim 12, wherein the semiconductor interconnect structure couples the channel region to a fixed potential.
14. The method of fabricating a sihcon on insulator circuit of claim 13, wherein the fixed potential is ground.
15. The method of fabricating a silicon on insulator circuit of claim 11 , wherein the semiconductor interconnect structure couples the field effect transistor to second circuit and protects the field effect transistor from ESD potential at the second circuit.
PCT/US2000/034212 2000-01-19 2000-12-13 Silicon on insulator circuit structure with buried semiconductor interconnect structure and method for forming same WO2001054174A1 (en)

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