KR940010384A - 박막트랜지스터 제조방법 - Google Patents

박막트랜지스터 제조방법 Download PDF

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Publication number
KR940010384A
KR940010384A KR1019920019541A KR920019541A KR940010384A KR 940010384 A KR940010384 A KR 940010384A KR 1019920019541 A KR1019920019541 A KR 1019920019541A KR 920019541 A KR920019541 A KR 920019541A KR 940010384 A KR940010384 A KR 940010384A
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KR
South Korea
Prior art keywords
semiconductor layer
insulating film
gate
forming
source
Prior art date
Application number
KR1019920019541A
Other languages
English (en)
Inventor
채기성
Original Assignee
이헌조
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이헌조, 주식회사 금성사 filed Critical 이헌조
Priority to KR1019920019541A priority Critical patent/KR940010384A/ko
Priority to JP26518293A priority patent/JP3420301B2/ja
Priority to US08/142,503 priority patent/US5403755A/en
Publication of KR940010384A publication Critical patent/KR940010384A/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

본 발명은 반도체소자 제조방법중 액정화면의 스위칭소자인 박막트랜지스터에 관한 것으로, 종래에는 절연막(2) 위에 반도체층을 형성한뒤 그 위에 게이트절연막(4)과 게이트 (6)를 형성하고 게이트(6)를 마스크로 이용하여 반도체층에 불순물이 온주입으로 소오스/드레인을 형성하였다.
따라서 누설전류가 발생하였다.
본 발명은 절연막위의 채널이될 영역에 반도체층(9)과 투명절연막(10)을 형성하고 양측에 소오스/드레인 영역인 저농도 n형 반도체층과 오농도 n형 반도체층을 형성하고 전면에 게이트절연막(13)을 형성한뒤 채널영역상에 게이트전극을 형성함으로 해소 반도체층과 소오스/드레인영역 사이의 전계차이가 감소되므로 누설전류를 최소화한다.

Description

박막트랜지스터 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 박막트랜지스터 공정단면도.

Claims (4)

  1. 절연막(8)위의 채널이될 영역에 반도체층(5)과 투명절연막(10)을 형성하는 제1공정과, 반도체층(5) 양측에 투명 절연막(10)에 걸쳐 소오스/드레인 영역인 저농도 제1도전형 반도체층(11)과 고농도 제1도전형반도체층(12)을 차례로 형성하는 제2공정과, 상기 투명절연막(10)을 제거하고 전면에 게이트절연막(13)을 형성하는 제3공정과, 상기 반도체층(9) 상측의 게이트절연막(13)위에 게이트전극(14)을 형성하는 제4공정과, 전면에 보호막(15)을 형성하고 보호막(15)과 게이트절연막(13)을 선택적으로 제하여 소오스/드레인전극 콘택홀을 형성하는 제5공정과, 콘택부위에 소오스/드레인전극(16)을 형성하는 제6공정으로 이루어짐을 특징으로 하는 박막트랜지스터 제조방법.
  2. 제1항에 있어서, 반도체층(9,11,12)은 다결정 실리콘으로 함을 특징으로 하는 박막트랜지스터 제조방법.
  3. 제1항에 있어서, 저농도 제1도전형반도체층(11)의 불순물 농도는 1×1012∼11×1013/㎠으로 함을 특징으로하는 박막트랜지스터 제조방법.
  4. 제1항에 있어서, 고농도 제1도전형반도체층(12)의 불순물 농도는 5×1014∼5×1015/㎠으로 함을 특징으로하는 박막트렌지스터 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920019541A 1992-10-23 1992-10-23 박막트랜지스터 제조방법 KR940010384A (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019920019541A KR940010384A (ko) 1992-10-23 1992-10-23 박막트랜지스터 제조방법
JP26518293A JP3420301B2 (ja) 1992-10-23 1993-10-22 薄膜トランジスタの製造方法
US08/142,503 US5403755A (en) 1992-10-23 1993-10-22 Method for fabricating a thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920019541A KR940010384A (ko) 1992-10-23 1992-10-23 박막트랜지스터 제조방법

Publications (1)

Publication Number Publication Date
KR940010384A true KR940010384A (ko) 1994-05-26

Family

ID=19341628

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920019541A KR940010384A (ko) 1992-10-23 1992-10-23 박막트랜지스터 제조방법

Country Status (3)

Country Link
US (1) US5403755A (ko)
JP (1) JP3420301B2 (ko)
KR (1) KR940010384A (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010015999A (ko) * 2000-09-06 2001-03-05 윤은혁 컴퓨터와 미싱기를 이용한 자수직물원단의 자수문양보수방법

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950021242A (ko) * 1993-12-28 1995-07-26 김광호 다결정 실리콘 박막 트랜지스터 및 그 제조 방법
JP3108296B2 (ja) 1994-01-26 2000-11-13 三洋電機株式会社 表示装置の製造方法
US5869360A (en) * 1996-09-26 1999-02-09 Micron Technology, Inc. Method for forming a thin film transistor
KR100271491B1 (ko) * 1998-05-19 2000-11-15 김순택 박막트랜지스터 제조방법
US6291255B1 (en) * 2000-05-22 2001-09-18 Industrial Technology Research Institute TFT process with high transmittance
JP5305630B2 (ja) 2006-12-05 2013-10-02 キヤノン株式会社 ボトムゲート型薄膜トランジスタの製造方法及び表示装置の製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5254488A (en) * 1988-01-04 1993-10-19 International Business Machines Corporation Easily manufacturable thin film transistor structures
EP0457596B1 (en) * 1990-05-17 1995-12-06 Sharp Kabushiki Kaisha Process for fabricating a thin film transistor
US5214295A (en) * 1992-01-28 1993-05-25 Micron Technology, Inc. Thin film field effect transistor, CMOS inverter, and methods of forming thin film field effect transistors and CMOS inverters
US5273920A (en) * 1992-09-02 1993-12-28 General Electric Company Method of fabricating a thin film transistor using hydrogen plasma treatment of the gate dielectric/semiconductor layer interface

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010015999A (ko) * 2000-09-06 2001-03-05 윤은혁 컴퓨터와 미싱기를 이용한 자수직물원단의 자수문양보수방법

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Publication number Publication date
US5403755A (en) 1995-04-04
JP3420301B2 (ja) 2003-06-23
JPH06209010A (ja) 1994-07-26

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