CN1160293A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN1160293A
CN1160293A CN96123937A CN96123937A CN1160293A CN 1160293 A CN1160293 A CN 1160293A CN 96123937 A CN96123937 A CN 96123937A CN 96123937 A CN96123937 A CN 96123937A CN 1160293 A CN1160293 A CN 1160293A
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金载甲
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MagnaChip Semiconductor Ltd
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Abstract

本发明披露了一种半导体器件及其制造方法。本发明的半导体器件包括：SOI晶片，它包括硅基片、形成于硅基片上部的绝缘膜、第一导电型硅层和形成于所述硅层与所述绝缘膜之间的传导层；形成于所述硅层的场氧化膜，它限定出第一和第二有源区；在所述第一有源区预定部分形成的栅电极；在所述栅电极两侧的第一有源区形成的第二导电型的源/漏区；在所述第二有源区形成的预定导电型的主体电极区。

Description

半导体器件及其制造方法
本发明涉及半导体器件及其制造方法，特别涉及没有基片浮置现象的SOI晶片及其制造方法。
通常，SOI(绝缘层上生长硅)晶片可防止因半导体器件的寄生电容所引起的RC延迟时间，以及接合区域的漏电流等，从而提供可形成低功耗和高速动作的器件用基片。
通过由形成了绝缘膜的器件晶片和支撑晶片进行粘附的方法，及向硅晶片深部注入氧离子而形成SIMOX(由注入的氧进行分离)的方法，制造这种SOI晶片。
现有技术如图3所示，制备由支撑基片1、绝缘层2及形成器件的硅层3组成的SOI晶片100。其中，硅层3为掺杂第一导电型杂质的膜层，为了防止形成于SOI晶片上的MOS(金属氧化物半导体)晶体管的击穿及短路现象，应形成厚度为约300～1500的硅层3。在该硅层3预定部分用公知的LOCOS方法形成场氧化膜4，从而限定出有源区。其中，场氧化膜4下部与绝缘层2接触，使形成元件的有源区完全被分隔。在硅层3上部顺序形成栅氧化膜5和多晶硅膜，对栅氧化膜5与多晶硅膜构图，从而形成栅电极6。在栅电极6和场氧化膜4之间的硅层3上离子注入第二导电型杂质，形成源/漏区7。其中，源/漏区7与绝缘层2接触，因而不会产生接触电容和泄漏电流。此后，在所得整个结构上部蒸镀预定厚度的层间绝缘膜8，进行蚀刻以露出源/漏区7，然后形成与源/漏区7接触的金属布线9。
可是，形成上述器件的硅层厚度为薄膜时，当沟道区完全被耗空之时，沟道区内的电位就会高于普通MOS晶体管的电位。而且，源区与沟道区间的电位位垒变低，在漏区侧的耗尽层中由碰撞离子生成的空穴在沟道区里暂时地堆积。此时，沟道区内的电位被提升，从源区开始向沟道区内急剧地注入电子，于是源、漏间的耐压变低，容易发生基片浮置现象。
因此，本发明的目的是提供一种半导体器件及其制造方法，即在不影响集成度的范围内，形成主体电极区，从而可防止在SOI基片上发生的基片浮置现象。
本发明包括：SOI晶片，它具有硅基片、形成于硅基片上部的绝缘膜、第一导电型硅层和在所述硅层与所述绝缘膜之间形成的传导层；形成于所述硅层，限定出第一和第二有源区的场氧化膜；形成于所述第一有源区预定部位的栅电极；形成于所述栅电极两侧的第一有源区的第二导电型源/漏区；以及形成于所述第二有源区的预定导电型主体电极区。
本发明半导体器件的制造方法，在SOI晶片上部制造存储器件的方法中，包括下列步骤：
提供形成有第一氧化膜的支撑基片；
提供形成有场氧化膜的器件基片，该场氧化膜限定出第一有源区和第二有源区；
在所述器件基片上部形成绝缘膜，以使所述第一和第二有源区的预定部位露出；
在绝缘膜上部形成传导层使其包含所述露出部分；
在所述传导层上部形成第二氧化膜；
所述器件基片的第二氧化膜与支撑基片的所述第一氧化膜表面接触，使所述器件基片与所述支撑基片接合；
蚀刻器件基片形成硅层，从而由所述支撑基片、硅层和所述基片与硅层之间的第一和第二氧化膜组成SOI晶片；
在所述沟道预定区域上部形成栅电极；
在所述硅层注入第二导电型杂质，在第一和第二有源区分别形成源/漏区和主体电极区。
下面，参照附图说明本发明实施例。
图1是按照本发明实施例在SOI晶片上形成的MOS晶体管(金属氧化物半导体晶体管)的剖面图；
图2A-2C是按照本发明实施例在SOI晶片上制造MOS晶体管的制造方法剖面图；
图3是现有SOI晶片上形成MOS晶体管的剖面图。
参见图1，在SOI基片200硅层的预定部分上，即硅层40的预定部分上形成场氧化膜31，该SOI晶片配置有硅支撑基片10、硅支撑基片10上部的氧化膜20和形成MOS晶体管的硅层40，从而限定出形成MOS晶体管的第一有源区AA和应形成主体电极区的第二有源区BB。其中，限定为第一有源区AA和第二有源区BB的硅层中掺有第一导电型、例如N型或P型杂质中的一种杂质。
在场氧化膜31之间的第一有源区AA形成栅氧化膜41和栅电极42。在栅电极两侧的第一有源区形成具有第二导电型的源/漏区43A、43B，在第二有源区形成主体电极区43C。其中，主体电极区43C与源/漏区43A、43B为同一种导电型，但其它实施例中也可为相反的导电型。
在硅层40与氧化膜20之间形成传导层33，由绝缘膜与硅支撑基片10绝缘。并且，传导层33由源/漏区43A、43B下部的绝缘膜32而与源/漏区43A、43B绝缘，源/漏区43A、43B之间的沟道区与主体电极区43C接触，即沟道区与主体电极区通过传导层33电气连接。其中，传导层33与形成器件的硅层40为含有同样的第一导电型杂质的硅层、多晶硅层或硅化物层。
图2示出按本发明实施例在SOI晶片上制造MOS晶体管的方法，因而，首先参见图2A，提供硅(Si)支撑基片10和器件基片30，硅支撑片形成有第一氧化膜20A、器件基片30具有预定的传导型。在由Si或GaAs组成的器件基片30的周边面的预定部分通过例如公知的LOCOS方法形成场氧化膜31。其中，按如下方式形成场氧化膜31，亦即可以限定形成有器件的第一有源区AA以及以后将形成主体电极的第二有源区BB。
在形成了场氧化膜31的器件基片30表面上，利用化学汽相淀积法淀积预定厚度的氧化膜32，然后，进行蚀刻，露出在第一有源区AA的器件沟道的预定区域和第二有源区BB的主体电极形成区域部分。
随后，形成传导层33，以使露出的器件基片30的沟道预定区和第二有源区BB的本体电极区域部分接触，该传导层33为与器件基片有同样导电类型，最好为硅层、多晶硅层、非晶硅或硅化物层。
在传导层33上部形成预定厚度的第二氧化膜20B，该氧化膜20B用作为形成SOI晶片的器件基片的埋置绝缘层，并为了使器件基片平坦化，对该露出的表面进行抛光。
本发明中，在支撑基片10上部形成用作SOI晶片埋置绝缘膜的第一氧化膜20A，在器件基片30上部形成用作SOI晶片埋置绝缘膜的第二氧化膜20B。
其它方法是，在器件基片30上部形成用作SOI基片埋置绝缘层的第一氧化膜20A，和在支撑基片10上部形成用作传导层33和SOI晶片的埋置绝缘膜的第二氧化膜20B。
如图2B所示，放置器件基片30和硅基片10，使器件基片的第二氧化膜20B和支撑基片的第一氧化膜20A接触，之后通过热处理工艺进行接合。接着，除去器件基片30，以使场氧化膜31A、31B的表面露出为止，从而形成器件用硅层40，即形成SOI基片200。不仅腐蚀器件基片30，并且进行化学的、机械的研磨清除，以使其表面平坦，从而形成硅层40。
如图2C所示，为了在硅层40形成器件，离子注入第一导电型、例如P或N型杂质，使其有导电性。然后，在硅层40上部形成厚150～200的栅氧化膜41，和在栅氧化膜上部形成预定厚度的多晶硅膜，接着，使多晶硅膜和栅氧化膜41构图，形成栅电极42。
在栅电极40两侧的第一有源区AA，离子注入第二导电型杂质，就形成源/漏区43A、43B，与此同时，在第二有源区BB离子注入第二导电型杂质，就形成主体电极区43C。因此，形成SOI晶片200上的MOS晶体管。
本发明实施例中，若硅层4和传导层33为N型，则源/漏区43A、43B就为P型。另一方面，若硅层40和传导层33为P型，则源/漏区43A、43B就为N型。此时，虽然主体电极区43C与源/漏区43A、43B为相同导电型，但在其它实施例中它们也可具有不同的传导型。
图2D是用于电连接上述MOS晶体管的金属布线工序的示意图，在形成MOS晶体管的硅层40上部形成预定厚度的层间绝缘膜44，进行刻蚀后，露出源、漏区43A、43B和主体电极区43C。然后，在该获得物表面上形成金属膜，以使金属膜与源、漏区43A、43B和主体电极区43C接触，对预定金属膜部分构图，于是形成电极布线45。
本发明中，虽然利用杂质掺杂的硅作连接沟道区和连接主体电极区的传导层，但是，使用可掺杂导电型物质，如多晶硅、非晶硅、硅化物膜等，也能获得与本发明相同的效果。
以上对本发明进行了详细说明，即在不影响集成度的范围内，形成主体电极区，防止了SOI晶片上发生的基片浮置现象，从而改善了SOI器件特性。

Claims (19)

1、一种半导体器件，其特征在于包括：
SOI晶片，它包括硅基片、在硅基片上部形成的绝缘膜、第一导电型硅层和在所述硅层与所述绝缘膜之间形成的传导层；
场氧化膜，它形成于所述硅层，并限定出第一有源区与第二有源区；
栅电极，它形成于所述第一有源区的所述硅层的预定部分；
第二导电型源/漏区，它形成于所述栅电极两侧的第一有源区；和
形成于所述第二有源区的所述硅层、与所述传导层接触的预定导电型的主体电极区。
2、如权利要求1的半导体器件，其特征在于，所述SOI基片的传导层为掺有预定导电型杂质的材料。
3、如权利要求2的半导体器件，其特征在于，所述传导层具有与所述硅层相同的导电型。
4、如权利要求2的半导体器件，其特征在于，所述传导层为选自硅层、多晶硅层、非晶硅和硅化物层中的一种。
5、如权利要求1的半导体器件，其特征在于，所述传导层为N型、所述源/漏区为P型。
6、如权利要求1的半导体器件，其特征在于，所述传导层为P型、所述源/漏区为N型。
7、如权利要求1的半导体器件，其特征在于，所述主体电极区与所述源/漏区有相同的导电型。
8、如权利要求1的半导体器件，其特征在于，所述SOI晶片还包括形成于源/漏区下部、使源/漏区与传导层分离的绝缘膜。
9、如权利要求8的半导体器件，其特征在于，所述绝缘膜为氧化膜。
10、一种半导体器件的制造方法，其特征在于在SOI晶片上部制造存储器件的方法中包括下列步骤：
提供有形成第一氧化膜的支撑基片；
提供形成了场氧化膜的器件基片，该场氧化膜限定出第一有源区和第二有源区；
在所述器件基片上部形成绝缘膜，以使所述第一和第二有源区的预定部分露出；
在绝缘膜上部形成传导层，使该传导层包含所述露出部分；
在所述传导层上部形成第二氧化膜；
使所述器件基片的第二氧化膜与支撑基片的所述第一氧化膜的表面接触，将所述器件基片与所述支撑基片接合；
蚀刻器件基片形成硅层，从而由所述支撑基片、硅层和所述基片与硅层之间的第一和第二氧化膜组成SOI晶片；
在所述沟道预定区域上部形成栅电极；
在所述硅层注入第二导电型杂质，在所述第一和第二有源区分别形成源/漏区和主体电极区。
11、如权利要求10的半导体器件制造方法，其特征在于，所述传导层与硅层具有相同的导电型。
12、如权利要求10的半导体器件制造方法，其特征在于，所述传导层由选自硅层、多晶硅层、非晶硅层和硅化物层中之一种形成的。
13、如权利要求10的半导体器件制造方法，其特征在于，在形成所述第二氧化膜的步骤与使所述器件基片和支撑基片接触的接合步骤之间，还包括附加的步骤，即使第二氧化膜平坦的平坦化工艺步骤。
14、如权利要求10的半导体器件制造方法，其特征在于，通过腐蚀工艺使所述第二氧化膜平坦化。
15、如权利要求10的半导体器件制造方法，其特征在于，通过化学的、机械的研磨方法使所述第二氧化膜平坦化。
16、如权利要求10的半导体器件制造方法，其特征在于，在形成所述S0I晶片的步骤与形成栅电极的步骤之间，还包括下面附加的步骤，即在SOI晶片的硅层上掺杂第一导电型杂质。
17、如权利要求10的半导体器件制造方法，其特征在于，在形成所述源/漏区和主体电极区的步骤之后，还包括下列步骤：
在硅层上部形成层间绝缘膜；
蚀刻层间绝缘膜，使所述源/漏区和主体电极区露出；
形成金属布线，使所述露出的源/漏区与主体电极区接触。
18、如权利要求10的半导体器件制造方法，其特征在于，所述第一导电型为P型杂质，第二导电型为N型杂质。
19、如权利要求10的半导体器件制造方法，其特征在于，所述第一导电型为N型杂质，第二导电型为P型杂质。
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