JP3189387B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having a dielectric isolation structure.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication (Kokai) No. 63-58817 discloses that a plurality of first semiconductor regions separated from each other by a separation groove with a groove insulating film are formed on a substrate insulating film formed on a surface of a semiconductor substrate. A semiconductor device having a dielectric isolation structure is manufactured by forming a second semiconductor region capable of conducting a substrate on the opening of the insulating film by epitaxial growth and filling the isolation groove with polysilicon at the same time.

[0003] This type of semiconductor device is suitable for an intelligent power device having a power element in a second semiconductor region and a high breakdown voltage integrated circuit in a first semiconductor region.

[0004]

However, when a semiconductor device having this kind of dielectric isolation structure is manufactured by the method disclosed in the above publication, it is necessary to fill the isolation trench with polysilicon in a high temperature environment suitable for epitaxial growth. In some cases, nests are formed in the polysilicon in the separation groove. When such nests are formed, the recesses during the manufacturing process are exposed, and for example, there is a problem that reliability is reduced due to, for example, disconnection of wiring and residue of dust or the like in the recesses. Although it is possible to reduce the number of cavities by performing annealing several times during the epitaxial growth and the filling of the polysilicon, the process becomes complicated and the characteristics of the epi region may be deteriorated. If the epitaxial growth temperature is reduced, the characteristics of the epi region deteriorate.

[0005] In particular, the above problem has become serious when miniaturization is attempted. This is because polysilicon having a large grain size is formed under a high temperature condition, and when the width of the separation groove is reduced by miniaturization, nests are more likely to be formed in the polysilicon in the separation groove. The present invention has been made in view of the above problems, and in a method for manufacturing a semiconductor device having an isolation region filled with polysilicon and an epi region, it is desirable to reduce nests contained in polysilicon in the isolation groove. , Its purpose.

[0006]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a semiconductor device is separated from each other by a separation groove having a substantially vertical side wall with a groove insulating film on a substrate insulating film formed on a surface of a semiconductor substrate. A first step of forming a plurality of first semiconductor regions, and a second step of forming a second semiconductor region capable of conducting a substrate by epitaxial growth on the opening of the substrate insulating film and filling the isolation trench with polysilicon. In the method for manufacturing a semiconductor device having the second step, the second step is a low-temperature step of forming a lower portion of the second semiconductor region capable of conducting a substrate by filling the separation groove and filling the separation groove and epitaxial growth, and thereafter, the second step is performed by epitaxial growth. A high temperature step of forming an upper portion of the second semiconductor region;
And thereafter flattening the surface portion. A method for manufacturing a semiconductor device according to a second aspect of the present invention provides a method for manufacturing a semiconductor device having a groove insulating film on a substrate insulating film formed on a semiconductor substrate surface.
A first step of forming a plurality of first semiconductor regions separated from each other by a separation groove having substantially vertical side walls; and forming a second semiconductor region capable of conducting a substrate by epitaxial growth on an opening of the substrate insulating film. A second step of filling the isolation groove with polysilicon, wherein the second step is a low-temperature step of filling the isolation groove with polysilicon, and a second step is performed thereafter to enable substrate conduction. (2) a step of selectively removing the polysilicon deposited in a region to be the semiconductor region and a substrate insulating film formed on the surface of the semiconductor substrate therebelow, and thereafter forming the second semiconductor region by high-temperature epitaxial growth And a step of flattening the surface portion thereafter.

[0007] The polysilicon buried in the isolation trench may be accompanied by amorphous silicon.

[0008]

As described above, in the method of manufacturing a semiconductor device according to the present invention, polysilicon is deposited under a condition lower than the temperature at the time of epitaxial growth to form a substantially vertically formed separation groove. After that, the second semiconductor region is completed by performing epitaxial growth at a high temperature, and thereafter, unnecessary silicon generated during the polysilicon deposition and epitaxial growth is removed to flatten the surface portion.

In this way, the nests in the separation groove can be reduced without deteriorating the electrical characteristics of the epitaxial growth region, ie, the second semiconductor region, and the separation groove filling step and the epitaxial growth step are performed in separate steps. Since the unnecessary silicon formed in step (1) is removed last, the process can be shortened.

[0010]

(Embodiment 1) FIG. 1 is a sectional view showing an embodiment of the present invention. In this semiconductor device, 1 is N
⁺ Silicon substrate (semiconductor substrate), 2 is a silicon oxide film (substrate insulating film), 3 and 4 are first semiconductor regions, 5 is a separation groove separating first semiconductor regions 3 and 4, and 6 is the surface of separation groove 5 A silicon oxide film (groove insulating film) formed on the substrate, 7 is polysilicon filled in the isolation groove 6, 8 is a second semiconductor region composed of an N ^- epi region, and G is a gate insulating film (not shown). It is a gate electrode. A PMOS transistor is formed in the first semiconductor region 3, and an NP transistor is formed in the first semiconductor region 4.
An N bipolar transistor is formed, and a vertical channel power MOS transistor is formed in the second semiconductor region 8. Note that the field insulating film, wiring, and the like are omitted in the above element.

Hereinafter, the manufacturing process of the above device will be described with reference to FIGS.
It will be described in detail with reference to FIG. First, as shown in FIG. 2, the N ⁺ diffusion layer 91 formed was resistivity 1~20Ω · cm N ^- -type (1
00) A single-crystal silicon substrate 92 was prepared, and a thermally oxidized silicon oxide film 2 was formed on the surface thereof to a thickness of 0.1 to 2 μm. Further, an N ⁺ -type (100) single crystal silicon substrate 1 containing a high concentration of impurities such as As is prepared by using H ₂ O ₂ -H ₂ SO
_{4 The} substrate 92 and 1 are combined at room temperature by heating in a mixed solution to perform a hydrophilic treatment.
Heat treatment was performed for minutes to 2 hours to join.

Subsequently, a predetermined thickness (for example, 0.5 to 3)
The substrate 92 is mirror-polished to 0 μm (5 μm in this embodiment) to produce an SOI substrate, an oxide film (not shown) is formed on the surface of the SOI substrate, and a predetermined mask pattern is formed by a normal photolithography process. Then, trench regions 5 and 50 reaching the silicon oxide film 2 were formed by dry etching. The trench region 5 is an isolation groove in the present invention, and the trench region 50 is an epi growth region for a power element (see FIG. 3). The trenches form single crystal first semiconductor regions 3 and 4 spatially separated from each other.

Subsequently, as shown in FIG. 4, a silicon oxide film 6 is formed to a thickness of 0.1 to 1 μm by thermal oxidation to insulate and protect the upper surfaces and side surfaces of each of the first semiconductor regions 3 and 4. The silicon oxide film 6 on the side is the groove insulating film according to the present invention.
Subsequently, the silicon oxide film 2 in the trench region 50 was removed to form a window 51, and the silicon substrate 1 was exposed. Subsequently, as shown in FIG. 5, a first deposition step (separation groove filling step in the present invention) is performed to grow a single-crystal N ^- epitaxial region on the exposed surface of the silicon substrate 1, Polysilicon layer 7 on oxide film 6 surface
1 is deposited. In this embodiment, the first deposition step is performed until the filling of the trench region 5 is completed.

What is important here is that the second layer is formed in order to prevent a nest from being formed in the polysilicon layer 71 in the trench region 5.
This is to lower the furnace temperature as much as possible within an allowable range of characteristic deterioration due to crystal defects in the semiconductor region 8. In this embodiment, the first deposition step is performed at a reduced pressure of 60 degrees Celsius.
It is carried out at 0 to 1050 degrees (preferably 950 degrees Celsius). Note that it is naturally possible to perform annealing during the deposition.

In this manner, since polysilicon having a small grain size is deposited, even if the width of the trench region 5 is 2 μm or less and the depth of the trench is 5 μm or more, the occurrence of nests can be prevented. Subsequently, a second deposition step (epitaxial growth step in the present invention) is performed to further grow a single crystal N ^- epitaxial region 82 on the epitaxial region 81 of the trench region 50. Two semiconductor regions 8 are formed.
The second deposition step is performed until the surface of the epitaxial region 82 is higher than the silicon oxide film 6 on the first semiconductor regions 3 and 4. Thus, a polysilicon layer 72 is formed on the polysilicon layer 71.

What is important here is that the second deposition step is performed at a high temperature of 1050 to 1200 degrees Celsius (here, 1150 degrees Celsius) in order to improve the electrical characteristics of the epitaxial region 82. By doing so, the deterioration of the electrical characteristics of the surface portion of the second semiconductor region 8 where the emitter, base, channel and the like are formed later is prevented. In addition, the polysilicon filling is completed completely even in the trench region 5 having a slightly wider width and not filled in the first deposition step (not shown).

Subsequently, as shown in FIG. 1, the surface was smoothed by selective polishing using the silicon oxide film 6 as a stopper (a flattening step in the present invention). Subsequently, a vertical channel power MOST is formed in the second semiconductor region 8 by an ordinary IC manufacturing process, and an NMOS is formed in the first semiconductor region 3.
T (not shown) and a PMOST were produced, and a bipolar transistor was produced in the first semiconductor region 4.

When the window 51 is formed in the present embodiment, the silicon oxide film 6 on the upper surfaces of the first semiconductor regions 3 and 4 can be selectively removed. In addition, if photoepitaxial growth by laser irradiation is employed in the first and second deposition steps, the substrate temperature can be reduced and the crystal quality can be improved. Further, in the first deposition step, low-temperature epitaxial growth (600 to 80
0 ° C.) can improve the crystal quality. (Embodiment 2) FIGS. 6 to 11 show the manufacturing process of another embodiment.

The device of this embodiment has the same structure as the device of the first embodiment shown in FIG. First, FIG.
Is formed, and the above-described first deposition step is performed thereon. In this case, the trench region 5
Since the 0 silicon oxide film 2 is not opened, a polysilicon layer 71 is also formed in the trench region 50. Therefore, this first deposition step is not restricted to the epitaxial growth temperature, but is performed at an optimum furnace temperature (here, 650 degrees Celsius) for reducing the grain size of the polysilicon layer 71.
The trench region 5 is filled with the polysilicon layer 71 without nests. At this time, if an impurity such as phosphorus is introduced into the polysilicon layer 71, the resistance is reduced.
Gettering can be performed reliably.

Subsequently, the window region 52 is formed by selectively etching the trench region 50 by a photolithography process. Here, the polysilicon layer 71 in the trench region 50 is removed by dry etching, and the underlying silicon oxide film 2 is removed by wet etching, exposing the single crystal silicon substrate 1. Next, the second deposition step described above is performed,
A single crystal N ^- epitaxial region 83 constituting the second semiconductor region was formed in the trench region 50. At this time, a polysilicon layer 72 is deposited on the polysilicon layer 71.

Subsequently, selective polishing was performed using the silicon oxide film 6 as a stopper in the same manner as in Example 1 to flatten the surface, thereby completing the main part of the process.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device to which a manufacturing method according to the present invention is applied;

FIG. 2 is a cross-sectional view showing a process of Example 1.

FIG. 3 is a cross-sectional view showing a process of Example 1.

FIG. 4 is a cross-sectional view showing a process of Example 1.

FIG. 5 is a cross-sectional view showing a process of Example 1.

FIG. 6 is a cross-sectional view showing a process of Example 2.

FIG. 7 is a cross-sectional view showing a process of Example 2.

FIG. 8 is a cross-sectional view showing a process of the second embodiment.

[Explanation of symbols]

1 is an N ⁺ silicon substrate (semiconductor substrate), 2 is a silicon oxide film (substrate insulating film), 3, 4 is a first semiconductor region, 5.5
0 is a trench region (isolation groove), 6 is a silicon oxide film
(Groove insulating film), 7 is polysilicon, 8 is a second semiconductor region,

Claims (2)

(57) [Claims] A first semiconductor region formed on a substrate insulating film formed on a surface of a semiconductor substrate and separated from each other by an isolation groove having a substantially vertical side wall with a groove insulating film;
A method of forming a second semiconductor region capable of conducting a substrate by epitaxial growth on an opening portion of the substrate insulating film and a second step of filling the isolation trench with polysilicon. The step is a low-temperature step of forming a lower portion of the second semiconductor region capable of conducting a substrate by filling the isolation trench and filling the isolation groove by epitaxial growth, and a high-temperature step of forming an upper portion of the second semiconductor region by epitaxial growth is performed thereafter. And a step of flattening the surface portion thereafter. 2. A method of forming a plurality of first semiconductor regions separated from each other by a separation groove having a substantially vertical side wall with a groove insulating film on a substrate insulating film formed on a surface of a semiconductor substrate.
A method of forming a second semiconductor region capable of conducting a substrate by epitaxial growth on an opening portion of the substrate insulating film and a second step of filling the isolation trench with polysilicon. Forming a low-temperature step of filling the isolation trench with polysilicon, and subsequently forming the polysilicon deposited in a region to become a second semiconductor region capable of conducting a substrate and the lower surface of the semiconductor substrate below the polysilicon; Manufacturing a semiconductor device, comprising the steps of: selectively removing the substrate insulating film that has been removed, forming the second semiconductor region by high-temperature epitaxial growth, and flattening a surface portion thereafter. Method.