JPH05347353A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to reduce cavities in an isolation trench without deteriorating electrical properties of a second semiconductor region by burying the isolation trench under cold conditions, then, forming the second semiconductor region, and eliminating unnecessary silicon to make the surface of that region smooth. CONSTITUTION:A method for manufacturing a semiconductor device has a first process for forming a plurality of first semiconductor regions 3 and 4, which are isolated from each other by an isolation trench 5 having a trench dielectric film 6, on a substrate dielectric film 2 formed on the surface of a semiconductor substrate 1. A second process includes an isolation trench filling process for burying the isolation trench 5 at a temperature lower than that at epitaxial growth and an epitaxial growth process for forming a second semiconductor region 8 which is practiced following the isolation trench filling process. The second process further includes a process for smoothing the surface of the second semiconductor region which is practiced after the epitaxial growth process. Thereby, cavities contained in a polysilicon layer 71 within the isolation trench 5 can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a dielectric isolation structure.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication No. Sho 63-58817 discloses a substrate insulating film formed on the surface of a semiconductor substrate, in which a plurality of first semiconductor regions separated from each other by a separation groove with a groove insulating film are formed. A semiconductor device having a dielectric isolation structure is manufactured by forming a second semiconductor region capable of conducting the substrate by epitaxial growth on the opening of the insulating film and filling the isolation trench with polysilicon at the same time.

This type of semiconductor device is suitable for an intelligent power device having a power element in the second semiconductor region and a high breakdown voltage integrated circuit in the first semiconductor region.

[0004]

However, when manufacturing a semiconductor device having this type of dielectric isolation structure by the method disclosed in the above publication, it is necessary to fill the isolation trench with polysilicon in a high temperature environment suitable for epitaxial growth. As a result, there were cases where cavities were formed in the polysilicon in the isolation trench. When such a nest is formed, the concave portion is exposed during the manufacturing process, and there is a problem that reliability is deteriorated due to, for example, disconnection of wiring and residual dust in the concave portion. It is possible to perform annealing many times during the epitaxial growth / polysilicon filling to reduce the cavities, but the process becomes complicated and the characteristics of the epi region may deteriorate. If the epitaxial growth temperature is reduced, the characteristics of the epi region will deteriorate.

In particular, the above problems have become serious when miniaturization is attempted. This is because polysilicon with a large grain size is formed under high temperature conditions, and as the width of the separation groove is reduced due to miniaturization, cavities are more likely to occur in the polysilicon within the separation groove. The present invention has been made in view of the above problems, and in a method of manufacturing a semiconductor device having an isolation trench filled with polysilicon and an epi region, it is possible to reduce the nests contained in the polysilicon in the isolation trench. , Its purpose is.

[0006]

According to a method of manufacturing a semiconductor device of the present invention, a plurality of first semiconductor regions separated from each other by a separation groove with a groove insulating film is formed on a substrate insulating film formed on a surface of a semiconductor substrate. A method for manufacturing a semiconductor device, comprising: a first step of forming the second insulating layer; and a second step of forming a second semiconductor region capable of conducting the substrate by epitaxial growth on the opening of the substrate insulating film and filling the isolation trench with polysilicon. The second step includes a separation groove filling step of filling the separation groove at a temperature lower than the temperature during the epitaxial growth, an epitaxial growth step of performing a second semiconductor region after the separation groove filling step, and an epitaxial growth step after the epitaxial growth step. And a flattening step of flattening the surface portion.

The polysilicon buried in the isolation trench can be accompanied by amorphous silicon.

[0008]

As described above, according to the method of manufacturing a semiconductor device of the present invention, polysilicon is deposited at a temperature lower than the temperature at the time of epitaxial growth to fill the isolation trench first, and then epitaxial growth is performed to make the second semiconductor. A region is formed, and then unnecessary silicon generated during the above polysilicon deposition and epitaxial growth is removed to flatten the surface portion.

[0009] With this structure, the voids in the isolation trench can be reduced without deteriorating the electrical characteristics of the epitaxial growth region, that is, the second semiconductor region, and the isolation trench filling step and the epitaxial growth step performed in separate steps. Since the unnecessary silicon formed in 1 is removed last, the process can be shortened.

[0010]

(Embodiment 1) A sectional view showing an embodiment of the present invention is shown in FIG. In this semiconductor device, 1 is N
⁺ Silicon substrate (semiconductor substrate), 2 is a silicon oxide film (substrate insulating film), 3 and 4 are first semiconductor regions, 5 is a separation groove for separating the first semiconductor regions 3 and 4, and 6 is a surface of the separation groove 5. A silicon oxide film (groove insulating film) formed on the substrate, 7 is polysilicon filled in the isolation trench 6, 8 is a second semiconductor region including an N ⁻ epi region, and G is on a gate insulating film (not shown). It is a gate electrode. A PMOS transistor is formed in the first semiconductor region 3, and an NP transistor is formed in the first semiconductor region 4.
N bipolar transistors are formed, and vertical channel power MOS transistors are formed in the second semiconductor region 8. It should be noted that the field insulating film, wiring, etc. are omitted from the above element.

The manufacturing process of the above device will be described below with reference to FIGS.
Will be described in detail. First, as shown in FIG. 2, the N ⁺ diffusion layer 91 formed was resistivity 1~20Ω · cm N ^- -type (1
00) A single crystal silicon substrate 92 was prepared, and a thermally oxidized silicon oxide film 2 was formed on its surface to a thickness of 0.1 to 2 μm. In addition, the N ⁺ type (100) single crystal silicon substrate 1 containing a high concentration of impurities such as As was used as H ₂ 0 ₂ —H ₂ SO.
₄ Heat in a mixed solution to perform hydrophilic treatment, combine the substrates 92 and 1 at room temperature, and heat at 30 ° C. at 600 to 1000 ° C.
Heat treatment was performed for about 2 minutes to 2 hours to bond them.

Subsequently, a predetermined thickness (for example, 0.5 to 3)
The substrate 92 is mirror-polished to 0 μm, 5 μm in this embodiment) to manufacture an SOI substrate, an oxide film (not shown) is formed on the surface of the SOI substrate, and a predetermined mask pattern is formed by a normal photolithography process. Then, trench regions 5 and 50 reaching the silicon oxide film 2 were formed by dry etching. The trench region 5 is an isolation groove according to the present invention, and the trench region 50 is an epi growth region for a power device (see FIG. 3). The trenches form single crystal first semiconductor regions 3 and 4 which are spatially separated from each other.

Subsequently, as shown in FIG. 4, a silicon oxide film 6 is formed by thermal oxidation to a thickness of 0.1 to 1 μm to insulate and protect the upper surfaces and side surfaces of the first semiconductor regions 3 and 4. The silicon oxide film 6 on the side surface is the groove insulating film in the present invention.
Subsequently, the silicon oxide film 2 in the trench region 50 was removed to form the window 51, and the silicon substrate 1 was exposed. Then, as shown in FIG. 5, a first deposition step (separation groove filling step in the present invention) is carried out to grow a single crystal N ⁻ epitaxial region on the exposed surface of the silicon substrate 1, and at the same time, silicon is formed. Polysilicon layer 7 on the surface of oxide film 6
1 is deposited. In this embodiment, this first deposition process is carried out until the filling of the trench region 5 is completed.

What is important here is that in order to prevent the formation of the nest in the polysilicon layer 71 in the trench region 5, the second
It is to reduce the temperature in the furnace as much as possible within the allowable range of characteristic deterioration due to crystal defects in the semiconductor region 8. In this example, the first deposition step was performed at a reduced pressure of 60 degrees Celsius.
It is carried out at 0 to 1050 degrees (preferably 950 degrees Celsius). It should be noted that it is naturally possible to perform annealing during the deposition.

In this way, since polysilicon having a small grain size is deposited, even if the width of the trench region 5 is 2 μm or less and the trench depth is 5 μm or more, generation of cavities can be prevented. Subsequently, a second deposition step (epitaxial growth step in the present invention) is performed to further grow a single crystal N ⁻ epitaxial region 82 on the epitaxial region 81 of the trench region 50. 2 The semiconductor region 8 is formed.
The second deposition process is performed until the surface of the epitaxial region 82 is located higher than the silicon oxide film 6 on the first semiconductor regions 3 and 4. In this way, the polysilicon layer 72 is formed on the polysilicon layer 71.

What is important here is that the second deposition step is performed at a high temperature of 1050 to 1200 ° C. (here, 1150 ° C.) in order to improve the electrical characteristics of the epitaxial region 82. By doing so, deterioration of the electrical characteristics of the surface portion of the second semiconductor region 8 in which the emitter, the base, the channel, etc. will be formed later is prevented. In addition, even in the trench region 5 having a slightly wider width and not completely filled in the first deposition process (not shown), the polysilicon filling is completely completed.

Subsequently, as shown in FIG. 1, the surface was smoothed by selective polishing using the silicon oxide film 6 as a stopper (planarizing step in the present invention). Subsequently, a vertical channel power MOST is formed in the second semiconductor region 8 by an ordinary IC manufacturing process, and an NMOS is formed in the first semiconductor region 3.
T (not shown) and PMOST were manufactured, and a bipolar transistor was manufactured in the first semiconductor region 4.

When the window 51 is formed in this embodiment, the silicon oxide film 6 on the upper surfaces of the first semiconductor regions 3 and 4 can be selectively removed. Further, when the optical epitaxial growth by laser irradiation is adopted in the first and second deposition steps, the substrate temperature can be lowered and the crystal quality can be improved. Further, in the first deposition step, low temperature epitaxial growth (600-80
The crystal quality can be improved by adjusting the temperature to 0 ° C. (Embodiment 2) Manufacturing steps of another embodiment are shown in FIGS.

The device of this embodiment has the same structure as the device of embodiment 1 shown in FIG. First, in the same process as in Example 1, FIG.
The semi-finished product shown in FIG. 1 is formed, and the above-mentioned first deposition step is performed thereon. In this case, the trench region 5
Since the silicon oxide film 2 of 0 is not opened, the polysilicon layer 71 is also formed in the trench region 50. Therefore, the first deposition step is not restricted by the epitaxial growth temperature, and the optimum furnace temperature (here, 650 degrees Celsius) for reducing the grain size of the polysilicon layer 71 is used.
Degree), so that the trench region 5 is filled with the non-nested polysilicon layer 71. At this time, if impurities such as phosphorus are introduced into the polysilicon layer 71, resistance is increased,
Gettering can be performed reliably.

Subsequently, the trench region 50 is selectively etched by a photolithography process to form a window 52. Here, the polysilicon layer 71 in the trench region 50 was removed by dry etching, and the silicon oxide film 2 thereunder was removed by wet etching to expose the single crystal silicon substrate 1. Next, the second deposition process described above is performed,
A single crystal N ⁻ epitaxial region 83 forming the second semiconductor region was formed in the trench region 50. At this time, the polysilicon layer 72 is deposited on the polysilicon layer 71.

Then, as in Example 1, selective polishing was performed using the silicon oxide film 6 as a stopper to flatten the surface, and the main part of the process was completed.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device to which a manufacturing method of the present invention is applied,

FIG. 2 is a cross-sectional view showing the process of Example 1,

FIG. 3 is a cross-sectional view showing a process of Example 1,

FIG. 4 is a cross-sectional view showing a process of Example 1,

FIG. 5 is a cross-sectional view showing the process of the first embodiment,

FIG. 6 is a cross-sectional view showing the process of Example 2;

FIG. 7 is a cross-sectional view showing a process of Example 2,

FIG. 8 is a cross-sectional view showing the process of Example 2;

[Explanation of symbols]

1 is an N ⁺ silicon substrate (semiconductor substrate), 2 is a silicon oxide film (substrate insulating film), 3 and 4 are first semiconductor regions, 5.5
0 is a trench region (separation groove), 6 is a silicon oxide film
(Groove insulating film), 7 is polysilicon, 8 is a second semiconductor region,

Claims (1)

[Claims] 1. A first step of forming a plurality of first semiconductor regions separated from each other by a separation groove having a groove insulating film on a substrate insulating film formed on a surface of a semiconductor substrate, and an opening portion of the substrate insulating film. In the method of manufacturing a semiconductor device, the method further comprises a second step of forming a second semiconductor region capable of conducting the substrate by epitaxial growth and filling the isolation trench with polysilicon, wherein the second step is higher than a temperature during the epitaxial growth. A separation groove filling step of filling the separation groove at a low temperature; an epitaxial growth step performed after the separation groove filling step to form a second semiconductor region; and a flattening step performed after the epitaxial growth step to flatten the surface portion. A method of manufacturing a semiconductor device, comprising: