JPS6339977Y2 - - Google Patents

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Publication number
JPS6339977Y2
JPS6339977Y2 JP17099183U JP17099183U JPS6339977Y2 JP S6339977 Y2 JPS6339977 Y2 JP S6339977Y2 JP 17099183 U JP17099183 U JP 17099183U JP 17099183 U JP17099183 U JP 17099183U JP S6339977 Y2 JPS6339977 Y2 JP S6339977Y2
Authority
JP
Japan
Prior art keywords
resistor
layer
substrate
insulating layer
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP17099183U
Other languages
Japanese (ja)
Other versions
JPS6079755U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17099183U priority Critical patent/JPS6079755U/en
Publication of JPS6079755U publication Critical patent/JPS6079755U/en
Application granted granted Critical
Publication of JPS6339977Y2 publication Critical patent/JPS6339977Y2/ja
Granted legal-status Critical Current

Links

Description

【考案の詳細な説明】 技術分野 本考案は、半導体基板の表面上に絶縁層を介し
て抵抗体層を有する半導体装置に関するものであ
る。
[Detailed Description of the Invention] Technical Field The present invention relates to a semiconductor device having a resistor layer on the surface of a semiconductor substrate with an insulating layer interposed therebetween.

従来技術 従来の典型的なモノリシツクICの抵抗はシリ
コン半導体基板内の拡散層によつて形成されてい
る。しかし、拡散層を利用して抵抗を形成する
と、基板の比抵抗によつて抵抗値が制限されるた
め、基板表面に絶縁層を介してSi多結晶層を形成
し、この多結晶層を抵抗として利用する技術が実
用化されるようになつた。この種の多結晶層を抵
抗とする従来の集積回路は、第1図及び第2図に
示す如く、シリコン半導体基板1の中に、例えば
n+型エミツタ領域2とp型ベース領域3とn型
コレクタ領域4とn+型接続領域5とから成るト
ランジスタ、及びp型領域6とn型領域7とから
成るダイオード等の半導体素子を形成し、半導体
基板1の上に酸化膜から成る絶縁層8を介してSi
多結晶抵抗体層9を形成し、絶縁層8の開孔1
0,11を介して抵抗体層9を基板1内の素子に
Alから成る導体層12,13で接続することに
よつて得られる。
Prior Art The resistor of a typical conventional monolithic IC is formed by a diffusion layer within a silicon semiconductor substrate. However, when a resistor is formed using a diffusion layer, the resistance value is limited by the specific resistance of the substrate. The technology used for this purpose has come into practical use. A conventional integrated circuit using this type of polycrystalline layer as a resistor has, for example,
Forming semiconductor elements such as a transistor consisting of an n + type emitter region 2, a p type base region 3, an n type collector region 4, and an n + type connection region 5, and a diode consisting of a p type region 6 and an n type region 7. Then, Si is deposited on the semiconductor substrate 1 via an insulating layer 8 made of an oxide film.
A polycrystalline resistor layer 9 is formed, and an opening 1 in an insulating layer 8 is formed.
The resistor layer 9 is connected to the element in the substrate 1 through 0 and 11.
This is obtained by connecting conductor layers 12 and 13 made of Al.

ところで、帯状に延びる抵抗体層9のパターン
と、導体層12,13のパターンとの位置ずれが
生じても、両者の電気的接続が十分得られるよう
に長さLの重なり合いの部分を設けなければなら
ない。特に、抵抗体層9をSi多結晶とし、導体層
12,13をAlとした場合には、両者の化合物
が形成し易いために、両者の接続面積即ち重なり
合いの長さLをある程度大きくすることが必要で
あつた。このため、ICの小型化が制限された。
なお、導体層12,13を設けないで、Si多結晶
抵抗体層9を基板1に直接に接続し、占有面積を
低減させることも考えられるが、Si基板1とSi多
結晶抵抗体層9とのコンタクトが不十分になるこ
と、及びSi多結晶抵抗体層9の導電型を基板1の
接続部の導電型に一致させなければならないこと
等の問題が生じる。
Incidentally, even if the pattern of the resistor layer 9 extending in a strip shape and the patterns of the conductor layers 12 and 13 are misaligned, an overlapping portion of length L must be provided so that sufficient electrical connection can be obtained between the two. Must be. In particular, when the resistor layer 9 is made of polycrystalline Si and the conductor layers 12 and 13 are made of Al, a compound of the two is likely to form, so the connection area between the two, that is, the overlapping length L, should be increased to some extent. was necessary. This has limited the ability to miniaturize ICs.
Note that it is possible to directly connect the Si polycrystalline resistor layer 9 to the substrate 1 without providing the conductor layers 12 and 13 to reduce the occupied area; Problems arise, such as insufficient contact with the Si polycrystalline resistor layer 9 and the need to match the conductivity type of the Si polycrystalline resistor layer 9 with the conductivity type of the connection portion of the substrate 1.

考案の目的 そこで、本考案の目的は、半導体基板表面上の
抵抗体及びその接続導体の占有面積を小さくする
ことが出来且つ抵抗体を確実に接続することが出
来る半導体装置を提供することにある。
Purpose of the invention Therefore, the purpose of the present invention is to provide a semiconductor device in which the area occupied by a resistor and its connecting conductor on the surface of a semiconductor substrate can be reduced, and the resistor can be reliably connected. .

考案の構成 上記目的を達成するための本考案は、半導体素
子が形成されている半導体基板と、前記基板の表
面上に形成され且つ開孔を有している絶縁層と、
前記絶縁層の上に形成され且つ抵抗本体部と接続
部とを有し且つ前記接続部が、少なくとも、前記
抵抗本体部に連続して前記開孔の周りに及ぶ部分
と前記抵抗本体部の一方の側に突出して前記開孔
の周りに及ぶ部分と前記抵抗本体部の他方の側に
突出して前記開孔の周りに及ぶ部分とを備えてい
る抵抗体層と、少なくとも前記開孔と前記抵抗体
層の前記接続部とを実質的に覆う部分を有して前
記抵抗体層を前記開孔を介して前記半導体素子に
接続する導体層とから成る抵抗を有する半導体装
置に係わるものである。
Structure of the Invention The present invention to achieve the above object includes: a semiconductor substrate on which a semiconductor element is formed; an insulating layer formed on the surface of the substrate and having an opening;
The resistor body is formed on the insulating layer and has a resistor body and a connecting portion, and the connecting portion is continuous with the resistor body and extends around the opening and one of the resistor body. a resistor layer including a portion that protrudes toward the other side of the resistor body portion and extends around the aperture, and a portion that protrudes toward the other side of the resistor body portion and extends around the aperture; and at least the aperture and the resistor. The present invention relates to a semiconductor device having a resistor including a conductor layer having a portion substantially covering the connection portion of the body layer and connecting the resistor layer to the semiconductor element through the opening.

考案の作用効果 上記考案によれば、抵抗体接続部に抵抗本体部
の一方及び他方の側に突出する部分を設けるの
で、導体層のパターンと抵抗体層のパターンとが
相対的にいずれの方向にずれても、両者の接続関
係を確保することが可能になる。
Effects of the device According to the above device, since the resistor connection portion is provided with a portion protruding to one side and the other side of the resistor body, the pattern of the conductor layer and the pattern of the resistor layer are relatively aligned in either direction. Even if there is a deviation, the connection relationship between the two can be maintained.

実施例 次に、第3図〜第8図を参照して本考案の実施
例に係わる抵抗を有するIC(集積回路)について
述べる。本実施例のICを製作する際には、まず、
第3図に示す如く、Si半導体基板1の中に、例え
ば、n+型エミツタ領域2とp型ベース領域3と
n型コレクタ領域4とn+型接続領域5とから成
るトランジスタ、及びp型領域6とn型領域7と
から成るダイオード等を半導体素子として形成す
る。また、基板1の表面上に厚さ1μmの熱酸化膜
から成る絶縁層8を形成し、その上にモノシラン
(SiH4)の熱分解によつて厚さ1μmのSi多結晶か
ら成る抵抗体層9を形成する。
Embodiment Next, an IC (integrated circuit) having a resistor according to an embodiment of the present invention will be described with reference to FIGS. 3 to 8. When manufacturing the IC of this example, first,
As shown in FIG. 3, a transistor consisting of, for example, an n + type emitter region 2, a p type base region 3, an n type collector region 4, an n + type connection region 5, and a p type A diode or the like consisting of region 6 and n-type region 7 is formed as a semiconductor element. Further, an insulating layer 8 made of a thermal oxide film with a thickness of 1 μm is formed on the surface of the substrate 1, and a resistor layer 8 made of polycrystalline Si with a thickness of 1 μm is formed on the insulating layer 8 by thermal decomposition of monosilane (SiH 4 ). form 9.

次に、第4図A及びBに示す如く、フオトエツ
チング法によつてメガネの枠状パターンに抵抗体
層9を残存させる。この抵抗体層9は、この実施
例ではn+型接続領域5とp型領域6との間に接
続されるものであり、これ等を結ぶ方向に延びて
いる帯状の抵抗本体部14と、この本体部14の
左右にそれぞれ設けられた第1及び第2の接続部
15,16とから成る。第1及び第2の接続部1
5,16には四角形の開孔17,18がそれぞれ
設けられている。この開孔17,18は、第5図
に示す絶縁層8の開孔10,11にほぼ一致する
ように形成されている。更に詳しく述べると、第
1の接続部15は、中央の抵抗本体部14に連続
していると共に開孔17に及ぶように形成された
右側部分15aと、抵抗本体部14の上側に突出
して開孔17を囲む上側部分15bと、抵抗本体
部14の下側に突出して開孔17を囲む下側部分
15cと、開孔17の左側を囲む左側部分15d
とを有している。右側の第2の接続部16も同様
に形成され、同様な部分16a,16b,16
c,16dを有する。なお、抵抗体層9の各部の
寸法を例示すると、中央の本体部14の長さ及び
幅がそれぞれ10μm、正四角形の開孔17,18
の各辺の長さがそれぞれ10μm、開孔17,18
を囲む接続部15の幅が5μmである。
Next, as shown in FIGS. 4A and 4B, the resistor layer 9 is left in the frame-shaped pattern of the glasses by photoetching. In this embodiment, this resistor layer 9 is connected between the n + type connection region 5 and the p type region 6, and includes a band-shaped resistor main body portion 14 extending in the direction connecting these. It consists of first and second connecting parts 15 and 16 provided on the left and right sides of this main body part 14, respectively. First and second connection parts 1
5 and 16 are provided with rectangular openings 17 and 18, respectively. The openings 17 and 18 are formed to substantially match the openings 10 and 11 of the insulating layer 8 shown in FIG. More specifically, the first connecting portion 15 includes a right side portion 15a that is continuous with the central resistor main body portion 14 and extends to the opening 17, and a right side portion 15a that protrudes above the resistor main body portion 14 and is open. An upper portion 15b surrounding the hole 17, a lower portion 15c protruding below the resistor body 14 and surrounding the hole 17, and a left side portion 15d surrounding the left side of the hole 17.
It has The second connecting portion 16 on the right side is formed in the same way, and includes similar portions 16a, 16b, 16.
c, 16d. In addition, to illustrate the dimensions of each part of the resistor layer 9, the length and width of the central main body part 14 are each 10 μm, and the square openings 17 and 18 are
The length of each side is 10μm, and the openings 17 and 18
The width of the connecting portion 15 surrounding the is 5 μm.

次に、第5図A,Bに示す如く抵抗体層9の開
孔17,18にほぼ一致するように絶縁層8にフ
オトエツチング法で開孔10,11を形成する。
Next, as shown in FIGS. 5A and 5B, openings 10 and 11 are formed in the insulating layer 8 by photoetching so as to substantially correspond to the openings 17 and 18 in the resistor layer 9.

次に、全面にAlを蒸着し、フオトエツチング
法で選択的にAl蒸着膜を除去することによつて
第5図に示す如く、四角形の導体層12,13を
形成する。なお、抵抗体層9の第1の接続部15
を覆うと共に開孔10,17を通して露出する基
板1の表面を覆うように第1の導体層12を形成
し、第2の導体層13も同様に形成する。
Next, Al is deposited on the entire surface and the Al deposited film is selectively removed by photo-etching to form rectangular conductor layers 12 and 13 as shown in FIG. Note that the first connection portion 15 of the resistor layer 9
The first conductor layer 12 is formed to cover the surface of the substrate 1 exposed through the openings 10 and 17, and the second conductor layer 13 is similarly formed.

基板1の表面上に抵抗を有するICを上述の如
く構成すれば、抵抗体層9のパターンに対して第
1の導体層12が第6図に示す如く左側にずれた
としても、上側部分15bと下側部分15cと左
側部分15dの上は導体層12によつて覆われる
ので、十分な接続が可能になる。また、第7図に
示す如く導体層12のパターンが下側にずれて
も、下側部分15c上を導体層12が覆うので、
十分な接続が可能になる。また、第8図に示す如
く、導体層12のパターンが斜め下にずれても、
接続を確保することが出来る。従つて、接続部1
5,16の左右方向の余裕を大幅に設けなくと
も、接続を十分に達成することが可能になり、基
板1の表面上における抵抗体層9と導体層12,
13との占有面積を小さくすることが可能にな
る。
If an IC having a resistor is configured as described above on the surface of the substrate 1, even if the first conductor layer 12 is shifted to the left with respect to the pattern of the resistor layer 9 as shown in FIG. Since the upper portions of the lower portion 15c and the left portion 15d are covered with the conductor layer 12, sufficient connection is possible. Furthermore, even if the pattern of the conductor layer 12 shifts downward as shown in FIG. 7, the conductor layer 12 covers the lower portion 15c.
Enables sufficient connectivity. Furthermore, as shown in FIG. 8, even if the pattern of the conductor layer 12 is shifted diagonally downward,
Connection can be secured. Therefore, connection part 1
5 and 16 in the horizontal direction, it is possible to achieve sufficient connection, and the resistor layer 9 and the conductor layer 12 on the surface of the substrate 1 can be easily connected.
It becomes possible to reduce the area occupied by 13.

変形例 本考案は上述の実施例に限定されるものではな
く、例えば、次の変形例が可能なものである。
Modifications The present invention is not limited to the embodiments described above, and, for example, the following modifications are possible.

(A) 第9図に示す如く、抵抗体層9の抵抗本体部
14と同じ幅の接続部15,16を長さL1
L2の範囲に設けてもよい。
(A) As shown in FIG .
It may be provided within the range of L2 .

(B) 開孔10,11,17,18の全部を囲むよ
うに接続部15,16を形成せずに、3方向の
部分15a,15b,15c及び16a,16
b,16cのみを設けてもよい。
(B) Portions 15a, 15b, 15c and 16a, 16 in three directions are formed without forming connecting portions 15, 16 so as to surround all of the openings 10, 11, 17, 18.
Only b and 16c may be provided.

(C) 開孔10,11,17,18を円形とし、接
続部15,16を例えば180度の角度範囲以上
にわたつて開孔10,11,17,18を囲む
ように形成してもよい。
(C) The openings 10, 11, 17, 18 may be circular, and the connecting portions 15, 16 may be formed to surround the openings 10, 11, 17, 18 over an angular range of 180 degrees or more, for example. .

(D) 基板1に対する接続を確実に達成するため
に、開孔10,11の大きさを開孔17,18
よりも幾分小さくしてもよい。
(D) In order to reliably achieve connection to the substrate 1, the sizes of the holes 10 and 11 are adjusted to the size of the holes 17 and 18.
It may be made somewhat smaller than that.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のICを示す平面図、第2図は第
1図のICの−線断面図、第3図〜第5図は
本考案の実施例に係わるICを製造工程順に示す
ものであり、第3図、第4図A、及び第5図Aは
断面図、第4図B及び第5図Bは平面図、第6
図、第7図、及び第8図は第5図のICに於ける
パターンのずれを示す平面図、第9図は変形例の
抵抗体層を示す平面図である。 1……半導体基板、8……絶縁層、9……抵抗
体層、10,11……開孔、12,13……導体
層、14……抵抗本体部、15,16……接続
部、17,18……開孔。
Fig. 1 is a plan view showing a conventional IC, Fig. 2 is a sectional view taken along the - line of the IC shown in Fig. 1, and Figs. 3 to 5 show ICs according to embodiments of the present invention in the order of manufacturing steps. Yes, Figures 3, 4A, and 5A are cross-sectional views, Figures 4B and 5B are plan views, and Figure 6
7, and 8 are plan views showing pattern deviations in the IC of FIG. 5, and FIG. 9 is a plan view showing a resistor layer of a modified example. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 8... Insulating layer, 9... Resistor layer, 10, 11... Opening, 12, 13... Conductor layer, 14... Resistor main body part, 15, 16... Connection part, 17, 18...Open hole.

Claims (1)

【実用新案登録請求の範囲】 (1) 半導体素子が形成されている半導体基板と、
前記基板の表面上に形成され且つ開孔を有して
いる絶縁層と、 前記絶縁層の上に形成され且つ抵抗本体部と
接続部とを有し且つ前記接続部が、少なくと
も、前記抵抗本体部に連続して前記開孔の周り
に及ぶ部分と前記抵抗本体部の一方の側に突出
して前記開孔の周りに及ぶ部分と前記抵抗本体
部の他方の側に突出して前記開孔の周りに及ぶ
部分とを備えている抵抗体層と、 少なくとも前記開孔と前記抵抗体層の前記接
続部とを実質的に覆う部分を有して前記抵抗体
層を前記開孔を介して前記半導体素子に接続す
る導体層と から成る抵抗を有する半導体装置。 (2) 前記抵抗体層はシリコン多結晶層である実用
新案登録請求の範囲第1項記載の半導体装置。
[Scope of claims for utility model registration] (1) A semiconductor substrate on which a semiconductor element is formed;
an insulating layer formed on the surface of the substrate and having an opening; and an insulating layer formed on the insulating layer and including a resistor main body and a connecting part, and the connecting part is at least connected to the resistor main body. a portion that extends around the aperture, a portion that protrudes to one side of the resistor body portion and extends around the aperture, and a portion that protrudes to the other side of the resistor body portion and extends around the aperture. a resistor layer having a portion substantially covering at least the opening and the connection portion of the resistor layer, the resistor layer is connected to the semiconductor through the opening; A semiconductor device having a resistor and a conductor layer connected to an element. (2) The semiconductor device according to claim 1, wherein the resistor layer is a silicon polycrystalline layer.
JP17099183U 1983-11-04 1983-11-04 Semiconductor device with resistance Granted JPS6079755U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17099183U JPS6079755U (en) 1983-11-04 1983-11-04 Semiconductor device with resistance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17099183U JPS6079755U (en) 1983-11-04 1983-11-04 Semiconductor device with resistance

Publications (2)

Publication Number Publication Date
JPS6079755U JPS6079755U (en) 1985-06-03
JPS6339977Y2 true JPS6339977Y2 (en) 1988-10-19

Family

ID=30373122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17099183U Granted JPS6079755U (en) 1983-11-04 1983-11-04 Semiconductor device with resistance

Country Status (1)

Country Link
JP (1) JPS6079755U (en)

Also Published As

Publication number Publication date
JPS6079755U (en) 1985-06-03

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