JP2792460B2 - Master slice LSI - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a master slice LSI, and more particularly to an analog master slice LSI.

[0002]

2. Description of the Related Art Conventionally, such an analog master slice L
The SI is created for the purpose of allowing a user to freely design all circuits using elements on a chip. In other words, this LSI has a configuration in which a resistor element and a transistor element are arranged on a chip, and a user creates all necessary circuits including a constant current source circuit using these arranged elements. I have.

FIG. 12 is a schematic configuration diagram of an analog master slice LSI showing an example of the related art. As shown in FIG. 12, a conventional analog master slice LSI 7 includes a transistor element 2 formed at the center of a chip,
a, 3b, a power supply wiring 4 and a GND wiring 5 are formed. The user can use these transistor elements 2
A desired circuit is formed by appropriately using the resistors 3a and 3b, the power supply wiring 4, and the GND wiring 5.

FIG. 13 is a general constant current source circuit diagram.
As shown in FIG. 13, transistors Q1 to Q4 connected between power supply wiring 4 and GND wiring 5 and resistance element R
1 (100 kΩ), R2 (5 kΩ), R3 (500 Ω)
In constructing the constant current source circuit composed of the following, when assembling using the respective elements of the master slice LSI of FIG. 12 described above, the layout is performed as shown in FIG. 14 below.

FIG. 14 is a layout diagram of the constant current source circuit shown in FIG. As shown in FIG. 14, this layout is a layout when the constant current source circuit shown in FIG. 13 is configured using the transistor element 2 and the resistance elements 3a and 3b on the chip in FIG. Here, the resistance element R1
In order to realize (100 kΩ), since the resistance value is large, a large number of resistance elements 3a must be connected in series. The terminals T1 and T2 are the voltage supply terminal T1 and the output terminal T2 in FIG.

[0006]

In the conventional analog master slice LSI described above, all circuits use resistor elements and transistor elements arranged on a chip.
Since the purpose is to allow the user to freely design, the constant current source circuit also needs to be configured with elements arranged on the chip, and there is a drawback that the use area of the user is narrowed.

Particularly, in the case of a resistance element, one large resistance of about 100 kΩ is required for each constant current source circuit, so that the use area of the resistance is greatly reduced. For example, a 100 kΩ resistor must be created by connecting 20 5 kΩ resistors in series.

Further, even when the constant current source circuit is prepared as a macro cell, the area occupied by the element is still large because the circuit is composed of elements arranged on a chip, and the area used by the user is still reduced. Would.

An object of the present invention is to provide a master slice LSI capable of reducing the burden on the circuit design of the user and improving the efficiency of the area used by the user.

[0010]

According to the master slice LSI of the present invention, a constant current source circuit including a first resistance element for determining a constant current value is formed only in a central portion of a chip , and is provided around the constant current source circuit. A transistor element to be formed; and a second resistance element formed together with a power supply wiring and a GND wiring outside the transistor element, wherein the constant current source circuit is diffused together with the transistor element and the second resistance element. The constant current source circuit created in the step
Close to both sides of the current source circuit and within the transistor element
A third resistance element is formed on the side at the stage of the diffusion .

[0011]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a schematic configuration diagram of a master slice LSI showing a first embodiment of the present invention. As shown in FIG. 1, the LSI chip 6 of this embodiment has one constant current source circuit 1 as shown in FIG. Note that this type of constant current source circuit 1 is used when drawing a current. Transistor elements 2 are arranged on both left and right sides of the constant current source circuit 1, and a resistor element 3
a, A resistive element 3b is arranged in the lower part. Further, the power supply wiring 4 is passed over the resistance element 3a, and the GND wiring 5 is passed between the transistor element 2 and the resistance element 3b.

The constant current source circuit 1 is simultaneously formed in a diffusion step for forming the transistor element 2 and the resistance element 3, and then only the wiring in the constant current source circuit 1 is formed in a normal wiring step. . Regarding this constant current source circuit 1,
The constant current source circuit 1 is formed using only one layer of wiring.
The wiring of the other circuits can be passed through the wiring area of the second layer.

FIG. 2 is a configuration diagram of the constant current source circuit in FIG. As shown in FIG. 2, the constant current source circuit 1 includes transistor elements Q1 to Q4 and resistance elements R1 to R3, as in the circuit of FIG. 13, and the internal wiring is omitted.
The area when this constant current source circuit 1 is configured on a chip is approximately 73000 μm 2, which is almost the same as the area occupied when configuring the resistance element R1 (100 kΩ) in FIG.

FIG. 3 is an enlarged configuration diagram of a portion including the constant current source circuit of FIG. As shown in FIG. 3, the resistance elements 3a, 3
The region b and the region of the transistor element 2 can be used as they are in circuit designs other than the constant current source circuit 1, and the efficiency is improved as compared with FIG. 14 described above. As shown in FIG. 2, the constant current source circuit 1 is a vertically elongated region. In addition, 4 is a power supply wiring and 5 is a GND wiring.

FIG. 4 is a schematic configuration diagram of a master slice LSI showing a second embodiment of the present invention. As shown in FIG. 4, this LSI chip 6 has one constant current source circuit 1 in the center of the chip, has transistor elements 2a in left and right separate areas, and has one NPN transistor element 2b and one PNP transistor element vertically. A region for the transistor element 2c is formed. In addition to the resistance elements 3a and 3b, resistance elements 3c are formed on the left and right sides in the immediate vicinity of the constant current source circuit 1. The constant current source circuit 1 and the NPN transistor elements 2b, PN
The P transistor element 2c and the resistance element 3c are simultaneously formed in the diffusion step. Here, the resistance element 3c is, for example, 1
One is formed by arranging ten resistance elements of 500Ω.

FIG. 5 is a circuit diagram of a constant current source created on the user side using the elements shown in FIG. As shown in FIG. 5, also in this embodiment, the transistor Q3 has wiring terminals T1 and T2 connected to the collector and the base. For this reason, the base of the transistor Q3 and FIG.
The constant current can be drawn from a plurality of blocks (circuits) by connecting the base of the NPN transistor element 2b disposed below the constant current source circuit 1 and using the resistance element 3c. The current value drawn from each of these blocks can be set by a combination of the NPN transistor element 2b and the resistance element 3c.

FIG. 6 is a configuration diagram of the constant current source circuit in FIG. As shown in FIG. 6, low resistance elements 3c are arranged on the left and right sides of a constant current source circuit 1 including transistors Q1 to Q4 and resistors R1 to R3, and are connected by wiring (not shown).

FIG. 7 is an enlarged view of a portion including the constant current source circuit of FIG. As shown in FIG. 7, this configuration is basically the same as FIG. 3, and as described in FIGS.
An NPN transistor element 2b, a PNP transistor element 2c and a resistance element 3c are added.

FIG. 8 is another constant current source circuit diagram created on the user side using the elements in FIG. As shown in FIG. 8, on the user side, the constant current source circuit 1 arranged at the center of the chip and built in
PN transistor element 2b, PNP transistor element 2
c and the resistance element 3c are added to create a target constant current source circuit. By using these PNP transistor elements 2c, a current can be supplied to each block, and by using the NPN transistor elements 2b, a current can be drawn from each block. Note that the value of the current flowing through each block can be freely set by a combination of these elements.

FIG. 9 is another constant current source circuit diagram in FIG. As shown in FIG. 9, this is a power supply circuit formed by using PNP transistor elements instead of bipolar transistors constituting the constant current source circuit 1. Therefore, the configuration when formed on a chip is the same as that in FIG.

FIG. 10 is a circuit diagram of still another constant current source created on the user side using the elements shown in FIG. FIG.
As shown by 0, here, it is designed independently on the user side using the element shown in FIG. 4 and the constant current source circuit 1 shown in FIG. That is, in addition to the constant current source circuit 1 of FIG.
PNP transistor element 2c and low-resistance resistance element 3c
And a constant current source circuit formed by using The function and the current value are the same as those in FIG.

FIG. 11 is a schematic configuration diagram of a master slice LSI showing a third embodiment of the present invention. As shown in FIG. 11, the LSI chip 6 of this embodiment has four constant current source circuits 1 formed therein. In particular, these constant current source circuits 1 are formed symmetrically, and the transistor element 2, the resistance element 3, the power supply wiring 4, and the GND wiring 5 are arranged therearound.

[0024]

As described above, in the master slice LSI of the present invention, by designing the constant current source circuit at the stage of diffusion, the design of this part can be made unnecessary, so that the burden on the user is reduced. There is an effect that can be. Further, according to the present invention, since the large resistance required for the constant current source circuit is formed without using the user area, there is an effect that the use efficiency of the user area can be improved.

[Brief description of the drawings]

FIG. 1 shows a master slice L according to a first embodiment of the present invention.
It is a schematic block diagram of SI.

FIG. 2 is a configuration diagram of a constant current source circuit in FIG.

FIG. 3 is an enlarged configuration diagram of a portion including the constant current source circuit of FIG. 1;

FIG. 4 shows a master slice L according to a second embodiment of the present invention.
It is a schematic block diagram of SI.

FIG. 5 is a circuit diagram of a constant current source using the elements shown in FIG.

FIG. 6 is a configuration diagram of a constant current source circuit in FIG.

FIG. 7 is an enlarged configuration diagram of a portion including the constant current source circuit of FIG.

8 is another constant current source circuit diagram using the elements in FIG.

FIG. 9 is another constant current source circuit diagram in FIG. 4;

FIG. 10 is a circuit diagram of still another constant current source using the element in FIG. 4;

FIG. 11 is a schematic configuration diagram of a master slice LSI showing a third embodiment of the present invention.

FIG. 12 shows an analog master slice L showing an example of the related art.
It is a schematic block diagram of SI.

FIG. 13 is a general constant current source circuit diagram.

FIG. 14 is a layout diagram of the constant current source circuit shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Constant current source circuit 2, 2a-2c Transistor element 3, 3a-3c Resistance element 4 Power supply wiring 5 GND wiring 6 LSI chip

Claims (1)

(57) [Claims] A constant current source circuit including a first resistive element for determining a constant current value is formed only in a central portion of a chip , and a transistor element is formed around the constant current source circuit; A second resistance element formed together with a power supply wiring and a GND wiring outside the element, wherein the constant current source circuit includes a constant current generated in a diffusion stage together with the transistor element and the second resistance element; Source circuit
A transistor element disposed on both sides of the constant current source circuit,
A master slice LSI , wherein a third resistive element is formed inside the substrate at the diffusion step .