JPH0982928A - Master slice integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve flexibility of an external terminal connecting position of a mounted circuit including resistance elements, in a master slice integrated circuit containing the resistance elements. SOLUTION: A gate array base board is constituted of a basic cell array 1 which is a regular arrangement of basic cells 11, pads 2 with resistance elements 5 buried in lower regions, a basic I/O buffer cell array 3 which is constituted by arranging basic I/O buffer cells 31 on a ring, and corner blocks 4. A mounted circuit is constituted of the basic cell 11, the pad 2, the basic I/O buffer cell 31, and a resistance element 5 buried in a lower region of the pad which is not connected with an external terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master slice integrated circuit, and more particularly to a master slice integrated circuit incorporating a resistance element.

[0002]

2. Description of the Related Art Conventionally, in a CMOS semiconductor integrated circuit, a circuit including a resistance element or a capacitance element has been used in addition to a logic gate and a sequential logic element. For example, FIG. 3 is a circuit diagram showing an oscillator circuit composed of a CMOS circuit. Further, FIG. 4 is an explanatory diagram showing an example of a means for realizing the resistance element of FIG. FIG. 4A is an explanatory view showing a resistance element using a diffusion layer, and FIG. 4B is an explanatory view showing a resistance element using an N-type MOS transistor having an extremely large channel length.

Referring to FIG. 3, this oscillator circuit comprises an inverter 6 used as an amplifier, a feedback resistor 5, and a crystal oscillator 9 connected via external terminals 81 to 82. In this case, it is desirable to make the wirings 51 to 52 connecting the inverter 6 and the feedback resistor 5 and the wirings 71 to 72 to the external terminals as short as possible. This is because if these wirings become long, the oscillation characteristics deteriorate due to the inductance and stray capacitance of the wiring portion.

However, the gate array (Gate)
Master slice (Master) such as Array
The Slice) integrated circuit has an internal structure in which basic cells having a fixed transistor size are arranged in an array. Further, this basic cell is for designing an ordinary logic gate, and from the viewpoint of operating speed and power consumption, the channel length L of the transistor used therein is set to the minimum value in the manufacturable range, and It is designed so that the resistance component of the diffusion layer is not attached as much as possible. When attempting to realize the resistance element of FIG. 4A or 4B using this basic cell, it cannot be realized without using many basic cells, and as a result, the wiring connecting the basic cells becomes very long and the inductance component And the capacitance component increases, and it becomes unsuitable as a resistance element for an oscillator. Therefore, a resistance element for an oscillator or the like is arranged as a dedicated resistance element in the corner portion of the chip.

FIG. 5 is a layout diagram showing a basic structure of a gate array which is a conventional master slice integrated circuit. Referring to FIG. 5, a conventional gate array is a basic I / O configured by arranging a basic cell array 1, a pad 2, and a basic I / O buffer cell 31 in which the basic cells 11 are regularly arranged on a ring. Buffer cell array 3,
The corner block 4 is included.

In the gate array, the portions of the basic cell array 1 and the basic I / O buffer cell array 3 are common regardless of the respective products, and what is called a function block is arranged on the common cell array 1 and the basic I / O buffer cell array 3, and both are arranged. The data is combined to achieve the desired function for each product. From the viewpoint of layout data, the data of the basic cell array 1 and the basic I / O buffer cell array 3 is mainly composed of the data up to the step before the metallizing step, and the data of the function block placed on the data is after the metallizing step. Has the data of. The connection between these function blocks is also made in the metallization process, and this data is generated by the automatic layout method.

The corner block 4 is arranged in the corner portion of the basic I / O buffer cell array 3, and the resistance element 5 is formed therein. Unlike the basic cell array 1, the area of the corner block 4 does not use this area to form a logic circuit, so that the transistor size can be freely designed. Therefore, the structure of either resistance element shown in FIG. 4 can be realized. Further, the inductance and the stray capacitance can be reduced as compared with the case where the internal basic cell is used.

FIG. 6 is a layout diagram showing an example of mounting an oscillator circuit by the gate array having the conventional structure shown in FIG. Referring to FIG. 6, the oscillator circuit includes an inverter function block 6, a resistor element 5, and an oscillator I / O.
It comprises a buffer block 7 and pads 21 and 22 connected to external terminals 81 and 82 of a master slice integrated circuit for connecting a crystal oscillator. In addition, the pad 21,
22 is via the oscillator I / O buffer block 7,
It is connected to the inverter function block 6 and the resistance element 5.

[0009]

However, in the gate array of this conventional structure, when the position of the pad connected to the external terminal of the oscillator is away from the corner portion, the wiring from the pad to the feedback resistance of the corner portion is provided. The length becomes longer, and the characteristics of the oscillator change due to the wiring capacitance and inductance. In order to avoid this, it is necessary to limit the position of the pad that can be used as an oscillator to a position close to the corner, and there is a problem that the external terminal connection position of the oscillator is also limited.

Therefore, the problem to be solved by the present invention is to improve the flexibility of the external terminal connection position of the mounted circuit including the resistance element in the master slice integrated circuit having the resistance element built therein.

[0011]

Therefore, the present invention provides a master slice integrated circuit having an array of basic cells and an array of pads arranged corresponding to external terminals and basic I / O buffer cells. A resistance element is embedded in a region below the pad.

Further, the mounted circuit is composed of the basic cell, the pad and the basic I / O buffer cell, and a resistance element embedded in a region below the pad which is not connected to the external terminal. There is.

For example, when the mounted circuit is an oscillator circuit, an amplifier including the basic cell and the basic I
The oscillator I / O buffer block is composed of a / O buffer cell, and a feedback resistance element composed of a resistance element embedded in a region below the pad that is not connected to the external terminal.

[0014]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a layout diagram showing one embodiment of a gate array which is a master slice integrated circuit of the present invention. Referring to FIG. 1, the gate array of this embodiment has a basic cell array 1 in which basic cells 11 are regularly arranged, a pad 2 in which a resistance element 5 is embedded in a region below, and a basic I / O buffer cell 31. Of the basic I / O buffer cell array 3 and the corner block 4. The corner block 4 does not include a resistance element.

FIG. 2 is a layout diagram showing an example of mounting an oscillator circuit having the gate array substrate structure shown in FIG.
Although only one oscillator is mounted in FIG. 2 for the sake of simplification of description, a function block for realizing a normal logic circuit is actually arranged in another basic cell array 1 portion. . Although the resistance element 5 is described only in the region under the pad 20, it actually exists in the region under all the pads as shown in FIG. 1, but the illustration is omitted in FIG.

The oscillator circuit shown in FIG.
1, an inverter function block 6, a basic I / O buffer cell 31, an oscillator I / O buffer block 7, a resistance element 5, and pads 21 and 22.

Inverter function block 6
Is arranged in the basic cell array 1 and is placed at a position closest to the oscillator I / O buffer block 7, and the wiring connecting these is connected at the shortest distance.

The oscillator I / O buffer block 7 is sized to occupy the three basic I / O buffer cells 31 corresponding to the pads 20, 21, 22 and is connected to the pads 21 and 22. Block terminal, connected to the resistance element 5 embedded in the area below the pad 20 2
It has one block terminal and two block terminals connected to the inverter function block 6.
The internal equivalent circuit is wiring between block terminals as shown in FIG. However, in practice, a circuit for protection against ESD and latch-up may be included in some cases.

The resistance element 5 is embedded in a region below the pad 20 which is not bonded. Therefore, the element characteristics are not deteriorated due to heat or pressure generated during bonding.

The pads 21 and 22 are pads bonded to external terminals for connecting the crystal oscillator. The resistive elements embedded in the area under these pads are not used.

As described above, in the case of the gate array substrate structure of the present embodiment, no matter which position the external terminal of the oscillator comes to, it is shown in FIG. 2 without changing the characteristics of the mounted oscillator circuit. It is possible to realize a different configuration.

In addition to the embodiment of FIG. 2, the pads 21 and 22 connected to the external terminals and the resistance element 5 are directly connected without the I / O buffer block 7 for the oscillator,
An embodiment in which the wiring length of the oscillator circuit is further shortened is also possible.

Further, in the description of the master slice integrated circuit of the present embodiment, the oscillator circuit is used as the mounting circuit including the resistance element, but the characteristics of the mounting circuit are changed even in the mounting circuit including other resistance elements. It is possible to freely set the position of the external terminal of the mounted circuit including the resistance element.

[0025]

As described above, in the master slice integrated circuit according to the present invention, since the resistance element is embedded in the region under the pad, when the circuit including the resistance element is mounted, the master slice integrated circuit is not bonded under the pad. The resistance element embedded in the region can be used, and the wiring length between the pad connected to the external terminal and the resistance element can always be minimized. Therefore, it is possible to prevent the characteristics of the mounted circuit including the resistance element from varying depending on the positions of the external terminals of the mounted circuit.

Further, since it is not necessary to limit the external terminal position of the mounted circuit including the resistance element, there is an effect that the flexibility of setting the external terminal position in response to a user request is improved.

[Brief description of drawings]

FIG. 1 is a layout diagram showing one embodiment of a master slice integrated circuit of the present invention.

FIG. 2 is a layout diagram showing an example of mounting an oscillator circuit by the master slice integrated circuit of FIG.

FIG. 3 is a circuit diagram showing an oscillator circuit which is an example of a mounted circuit including a resistance element.

FIG. 4 is an explanatory diagram showing an example of means for realizing the resistance element of FIG.

FIG. 5 is a layout diagram showing a basic structure of a conventional master slice integrated circuit.

6 is a layout diagram showing an example of mounting an oscillator circuit by the master slice integrated circuit of FIG.

[Explanation of symbols]

1 Basic Cell Array 11 Basic Cell 2, 20-22 Pad 3 Basic I / O Buffer Cell Array 31 Basic I / O Buffer Cell 4 Corner Block 5 Resistance Element or Feedback Resistance Element 51-52, 71-72 Wiring 6 Inverter or Function for Inverter Block 7 Oscillator I / O buffer block 81-82 External terminal 9 Crystal oscillator

Claims (3)

[Claims] 1. A master slice integrated circuit having an array of basic cells and an array of pads arranged corresponding to external terminals and basic I / O buffer cells, wherein a resistance element is provided in a region below the pads. Embedded therein is a master slice integrated circuit. 2. A circuit comprising the basic cell, the pad and the basic I / O buffer cell, and a resistance element embedded in a region below the pad that is not connected to the external terminal is mounted. Item 2. A master slice integrated circuit according to item 1. 3. An amplifier composed of the basic cell, an oscillator I / O buffer block composed of the basic I / O buffer cell, and a resistance element embedded in a region below a pad not connected to the external terminal. The master slice integrated circuit according to claim 1, further comprising an oscillator circuit including a feedback resistance element.