JPH08125149A - Production of semiconductor device and photomask - Google Patents

Abstract

PURPOSE: To produce wafers of a plurality of kinds of circuit scale using a single photomask by arranging an I/O buffer part, including a pad part, in the central region of a photomask and forming a circuit element while setting an exposing region of the photomask arbitrarily depending on the scale of circuit. CONSTITUTION: An I/O buffer part 2 including a pad part is provided in the central region of a photomask 1. An X-direction alignment pattern 4 and a Y-direction alignment pattern 5 are arranged on the periphery of the I/O buffer part 2. A basic circuit element part 3 entirely arranged with gates is provided at other region. The basic circuit element part 3 has an area corresponding to the maximum possible scale of the mask 1. When the exposing region of the photomask 1 is varied depending on the scale of gate thus varying the region of the basic circuit element part 3, a master slice corresponding to a desired scale of gate can be obtained. Consequently, wafers of plurality of kinds of circuit scale can be formed using a single photomask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device such as a gate array.

[0002]

2. Description of the Related Art A manufacturing process of a semiconductor device called a gate array includes a basic process (a process of forming a large number of basic circuit elements) and a wiring process (a process of connecting basic circuit elements so as to perform a desired circuit operation). Is roughly divided into Here, the wafer manufactured in the basic process is a master slice (base wafer)
is called. The gate array has the advantage that various kinds of circuits can be obtained by applying various wiring to the same basic circuit, and can be manufactured in a short period of time as compared with general semiconductor devices manufactured in the basic process each time. ing.

FIG. 9 shows a photomask used for forming a conventional master slice, and FIG. 10 shows a gate array chip obtained by using the photomask shown in FIG.

In FIG. 9, a photomask 21 for manufacturing a master slice is provided with a basic circuit element portion 23 having a desired gate scale in the central region, and an input / output buffer portion 22 including a pad portion on the outer periphery thereof. Are arranged. Further, on the outer periphery of the input / output buffer unit 22, X
Direction alignment pattern 24 and Y direction alignment pattern 2
And a scribe line region 27 including 5 are formed. Using such a photomask 21, the photomask 21
The master slice is manufactured by patterning the entire surface as an exposure area. Then, by connecting the basic circuit elements with metal wiring such as aluminum so as to perform a desired circuit operation with respect to the master slice, as shown in FIG.
It is possible to obtain the gate array chip 26 as shown in FIG. Wiring patterns are not shown in FIGS. 9 and 10.

In the method of manufacturing a gate array as described above, when the desired gate scale is different, photomasks of different exposure sizes are created and patterned according to the gate scale. Therefore, photomasks for master slices must be created for each different number of gates used, and when creating multiple sets of master slices, the more master slices that are manufactured, the more photomasks are manufactured. There was a problem that the cost increased.

In order to solve the above problems, for example, in a known example disclosed in Japanese Patent Laid-Open No. 4-223324, a photomask 21 for a basic process as shown in FIG. 11C is used.
By using the basic circuit element 2 as shown in FIG.
Create a master slice in which 3 is spread all over the wafer,
After that, by using the photomask 22 having the chip exposure pattern 25 as shown in FIG. 11D on the basic circuit element 23, the wiring, the input / output buffer, and the chip 24 as shown in FIG. Forming a pad. In this way, a method of reducing the number of types of master slices and reducing the number of photomasks 21 for master slices has been proposed. Further, in another example disclosed in Japanese Patent Laid-Open No. 61-94341, as shown in FIG. 12A, three types of basic circuits having a basic circuit element pattern 34 and an input / output buffer pattern 35 are provided. The number of master-slice photomasks can be increased by creating typical photomasks 31 to 33, and by combining the photomasks with various different gate scales as shown in FIG. 12B or FIG. 12C. Have been proposed.

[0007]

However, in the conventional method for manufacturing a semiconductor device as described above, the method disclosed in Japanese Patent Laid-Open No. 4-22 is used.
In the known example of Japanese Patent No. 3324, a master slice in which basic circuit elements are spread over the entire surface of a wafer is created in a basic step, and a photomask having a chip exposure pattern is used on the basic circuit elements to perform wiring on a chip, Although I / O buffers and pads are formed, the gates used in I / O buffers usually have a complicated circuit structure to improve surge resistance and prevent latch-up. It needs to be designed several times larger than a large gate. Therefore, if an attempt is made to obtain the circuit configuration of the input / output buffer from the basic circuit elements, the wiring resistance is increased because the wiring is connected, and the characteristic deterioration occurs as compared with the conventional input / output buffer, and the yield is reduced. is there. Further, there is a drawback that the pattern area of the input / output buffer section becomes large, so that the feasibility is poor.

On the other hand, in the example of Japanese Patent Laid-Open No. 61-94341, since three photomasks are used in the process of forming the master slice, there is a drawback that the time required for the basic process becomes long. Further, when the alignment is performed using three photomasks, the misalignment direction and the amount are different for each of the photomasks a, b, and c, so that this pattern is locally formed in one chip in the wiring process. Target (eg Figure 1
There was a possibility that the amount of misalignment would be large in the A and B parts of 2 (b) and the yield would be reduced.

The present invention has been made in order to solve the problems of the above-described conventional techniques, and reduces the photomask for producing the master slice to reduce the photomask manufacturing cost and the wafer manufacturing cost. Another object of the present invention is to provide a method for manufacturing a semiconductor device, which shortens the time required for manufacturing a photomask.

[0010]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention uses a photomask to form an input / output buffer including circuit elements and pads on a wafer. In the manufacturing method, an exposure area of the photomask is arbitrarily set according to a circuit scale to form an input / output buffer including the circuit element and the pad.

At this time, an input / output buffer portion for forming an input / output buffer including the pad may be arranged in a central region of the photomask, and an input / output buffer portion including the pad may be provided in a peripheral portion of the input / output buffer portion. A second input / output buffer unit for forming an output buffer may be arranged.

The photomask used in the present invention is
In a photomask having a basic circuit element part for forming a circuit element on a wafer and an input / output buffer part for forming an input / output buffer including a pad, the input / output buffer part is arranged in a central region. Is characterized by.

At this time, a second input / output buffer section for forming an input / output buffer including the pad may be arranged around the input / output buffer section.

[0014]

According to the method of manufacturing a semiconductor device of the present invention configured as described above, for example, an input / output buffer section including a pad section is arranged in a central area of a photomask, and an exposure area of the photomask is arranged in accordance with a circuit scale. By forming circuit elements by setting them arbitrarily, it becomes possible to manufacture a plurality of types of wafers having a circuit scale with one photomask.

Further, in the photomask of the present invention configured as described above, the exposure area can be arbitrarily set according to the circuit scale by disposing the input / output buffer section including the pad section in the central area. It will be possible.

[0016]

Embodiments of the present invention will now be described with reference to the drawings.

(First Embodiment) First, the case of creating a master slice having a 200K gate scale and a 300K gate scale will be described.

FIG. 1 is a diagram showing a first embodiment of the photomask of the present invention.

As shown in FIG. 1, in the mask pattern of the photomask 1 used in this embodiment, an input / output buffer portion 2 including a pad portion is provided in the mask central region (for example, about 3 mm □). An X-direction alignment pattern 4 and a Y-direction alignment pattern 5 are arranged around the input / output buffer unit 2.
The rest of the area is the basic circuit element part 3 with gates
Is provided. Further, the basic circuit element section 3 has an area corresponding to the maximum scale that can be created by the photomask 1, for example, a gate scale of about 700K. In such a configuration, the size of the exposure region of the photomask 1 is changed according to the desired gate scale, and the basic circuit element portion 3
It is possible to obtain a master slice corresponding to a desired gate scale by changing the area of.

Next, using the photomask of this embodiment, 2
The case of creating a master slice of 00K gate scale will be described. As shown in FIG. 2, the exposure area 8 is set so that a master slice having a 200K gate scale can be obtained with respect to the photomask 1 shown in FIG. The exposure area 8 includes an input / output buffer section 2 including a pad section arranged in the central area of the photomask 1, an X-direction alignment pattern 4, a Y-direction alignment pattern 5, and a basic circuit element section 3. ing.

Incidentally, with respect to the eight sizes of the exposure area,
The scribe line region can be set in the master slice by setting the step pitch of the reduction projection exposure apparatus to be large, for example, about 50 μm per side.

By forming a pattern in the exposure area 8 as described above, a master slice of 200K gate scale can be obtained, and the basic circuit element portion 3 is connected by metal wiring such as aluminum so as to perform a desired circuit operation. Therefore, Fig. 3
It is possible to obtain a gate array chip 6 having a 200K gate scale as shown in FIG.

On the other hand, in the case of creating a master slice of 300K gate scale, as shown in FIG. 4, the exposure area 9 is obtained so as to obtain a master slice of 300K gate scale mounted on the photomask shown in FIG. To set. Then, by patterning the exposure region 9 using the above photomask, a master slice of 300K gate scale can be obtained.

Then, by connecting the basic circuit elements with a metal wiring such as aluminum so that the master slice of 300K gate scale can perform a desired circuit operation, the gate array chip 7 of 300K gate scale as shown in FIG. 5 is mounted.
Can be obtained. Wiring patterns are not shown in FIGS.

In this embodiment, 200K gate scale, 300
The pattern forming method of each gate array of K gate scale has been described. However, when a master slice with a larger gate scale (up to 700K) is desired, the exposure area of the photomask 1 shown in FIG. 1 is enlarged to form each pattern. Should be done. In addition, the gate array created by using the photomask 1 can be assembled and mounted by connecting the electrode portion of the mounting package and the bonding pad with the bump tab.
A desired semiconductor device can be obtained.

As described above, since the input / output buffer section 2 including the pad section is arranged in the central area of the photomask 1, the exposure area of the photomask 1 can be arbitrarily set and patterned according to the desired gate scale. Can be 1
It is possible to manufacture master slices having different gate scales with one photomask 1. Therefore, the manufacturing cost of the photomask 1 and the manufacturing cost of the master slice are reduced, and the time required for manufacturing the photomask 1 is omitted, so that the development time of the gate array is shortened.

(Second Embodiment) FIG. 6 is a view showing a second embodiment of the photomask of the present invention. As shown in FIG. 6, the photomask 11 used in this embodiment has a mask center (up to 3).
First input / output buffer section 12 including a pad section in mm
And a second input / output buffer section 16 having a side of about 12 mm and a width of about 500 μm is arranged in a rectangular shape with the center of the photomask 11 as the center.

Further, the X-direction alignment pattern 14 is provided on the outer periphery of the first input / output buffer section 12 including the pad section.
The Y-direction alignment pattern 15 and the first basic circuit element section 13 are arranged, and further, the second basic circuit element section 17 is arranged on the outer periphery of the second input / output buffer section 16. The total gate scale of the first basic circuit device section 13 and the second basic circuit device section 17 is a fixed size (for example, 1000) regardless of the desired gate scale.
Layout in K).

Even in such a structure, as shown in FIG. 7, the exposure region 18 of the photomask 11 is set according to a desired gate scale, and patterning is performed.
Master slices having different gate scales can be obtained with one photomask 11. In addition, since the present embodiment has the first input / output buffer section 12 and the second input / output buffer section 16 including the pad section, the area of the input / output buffer section is larger than that of the first embodiment. This is suitable when the desired gate scale is large and the number of pads is large. When the master slice is obtained, the first basic circuit element section 13 is formed by metal wiring such as aluminum so as to perform a desired circuit operation.
By connecting the second basic circuit element section 17, a gate array chip 19 as shown in FIG. 8 can be obtained.
Further, the wiring pattern is not shown in FIGS.

In this embodiment, the second portion including the pad portion is used.
Although the input / output buffer section 16 is arranged in a rectangular shape, for example, the second input / output buffer section 16 is arranged on the diagonal line of the mask in the same shape as the first input / output buffer section 12, or If the input / output buffer portions are arranged in the central region of the photomask 11 and its peripheral portion, for example, by arranging a plurality of input / output buffer portions having the same shape as the input / output buffer portion 16 of No. 2, the present embodiment. Similarly, one photomask 11 can obtain master slices having different gate scales.

Although the above embodiments have been described with reference to the gate array, it goes without saying that the present embodiment can be applied to not only the gate array but also other custom ICs such as PLA.

[0032]

Since the present invention employs the method as described above, the following effects can be obtained.

By arranging the input / output buffer section including the pad section in the central area of the photomask, the exposure area of the photomask can be arbitrarily set according to the desired circuit scale of the wafer to form the circuit element. Since it becomes possible, a plurality of types of circuit-scale wafers can be created with one photomask. Therefore, the photomask manufacturing cost and the wafer manufacturing cost are reduced and the time required for manufacturing the photomask is omitted, so that the development time of the semiconductor device is shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of a photomask of the present invention.

FIG. 2 is a diagram showing an exposure region when a master slice of 200K gate scale is created using the photomask of FIG.

FIG. 3 is a 200 obtained using the photomask of FIG.
It is a figure which shows the gate array chip of K gate scale.

FIG. 4 is a diagram showing an exposure region when a master slice of 300K gate scale is formed using the photomask of FIG.

FIG. 5: 300 obtained using the photomask of FIG.
It is a figure which shows the gate array chip of K gate scale.

FIG. 6 is a diagram showing a second embodiment of the photomask of the present invention.

FIG. 7 is a diagram showing an exposure region when a master slice is created using the photomask of FIG.

FIG. 8 is a diagram showing a gate array chip obtained by using the photomask of FIG.

FIG. 9 is a photomask used to create a conventional master slice.

10 is a diagram showing a gate array chip obtained using the photomask of FIG. 9. FIG.

11A and 11B are diagrams illustrating an example of a conventional method for manufacturing a semiconductor device, FIG. 11A is a wafer diagram on which a basic circuit element is formed, and FIG. 11B is a wafer diagram on which chips are formed; Further, FIG. 7C is a photomask diagram for forming a basic circuit element, and FIG. 8D is a photomask diagram for forming a chip.

12A and 12B are diagrams illustrating an example of a conventional method for manufacturing a semiconductor device, in which FIG. 12A is a photomask diagram and FIG.
And FIG. 6C is a diagram showing an example of a combination of photomasks.

[Explanation of symbols]

 1, 11 Photomask 2 Input / output buffer section 3 Basic circuit element section 4, 14 X-direction alignment pattern 5, 15 Y-direction alignment pattern 6, 7, 19 Gate array chip 8, 9, 18 Exposure area 12 First Input / output buffer section 13 First basic circuit element section 16 Second input / output buffer section 17 Second basic circuit element section

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device in which an input / output buffer including a circuit element and a pad is formed on a wafer by using a photomask, wherein an exposure region of the photomask is arbitrarily set according to a circuit scale. Forming a I / O buffer including the circuit element and the pad. 2. The semiconductor device manufacturing method according to claim 1, further comprising: disposing an input / output buffer portion for forming an input / output buffer including the pad in a central region of the photomask. Device manufacturing method. 3. The method of manufacturing a semiconductor device according to claim 2, wherein a second input / output buffer section for forming an input / output buffer including the pad is arranged in a peripheral portion of the input / output buffer section. A method for manufacturing a semiconductor device, comprising: 4. A photomask having a basic circuit element portion for forming a circuit element on a wafer and an input / output buffer portion for forming an input / output buffer including a pad, wherein the input / output buffer portion is in the center. A photomask characterized by being arranged in a region. 5. The photomask according to claim 3, wherein a second input / output buffer section for forming an input / output buffer including the pad is arranged around the input / output buffer section. Photomask to do.