JPH10335205A - Pattern design method of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a time required for EB processing and its verification process by a method wherein at least one of alignment patterns is provided inside a dicing pattern. SOLUTION: A pattern 6A where a slide gauge is provided is arranged in dicing marks 4 located on the right of and below a scribe line 10 respectively. That is, two pellet regions 5 are arranged in an X direction and a Y direction respectively, the dicing mark 4 is provided to the intersections of the scribe lines 10 and the corners of the pellet regions 5 respectively, and another alignment pattern is provided to the center of the scribe lines 10. One out of alignment patterns or a pattern 6A where a slide gauge pattern and a dicing mark 4 are provided in one piece is provided on an X axis and a Y axis of all the data respectively. By this setup, the component cells of pattern data are reduced in number, all the data are lessened in volume, an EB processing time is shortened, and the verification operation of drawing data after EM processing is carried out can be lessened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of designing a pattern of a semiconductor integrated circuit, and more particularly to a method of designing a positioning pattern for forming a circuit element and a dicing pattern used for wafer cutting.

[0002]

2. Description of the Related Art A conventional pattern designing method of this type will be described with reference to the drawings. FIG. 6 is a pattern diagram for explaining this type of conventional pattern design method.

In FIG. 6, reference numeral 1 denotes an alignment pattern (hereinafter, referred to as a wafer alignment mark) for aligning a wafer with an exposure apparatus in a stepper type exposure apparatus, and reference numeral 2 denotes alignment of a wafer with a reticle on which a layout pattern is drawn. Pattern (hereinafter referred to as a laser stepper alignment mark), 3 is a pattern (hereinafter referred to as a vernier caliper pattern) for confirming whether or not there is a deviation from the pattern formed in the previous step in each manufacturing process, and 4 is a wafer. This is an alignment pattern (hereinafter referred to as a dicing mark) used for positioning the wafer and the cutting device when cutting into pellets.
These patterns have been arranged on a reference line (scribe line) 10 arranged around the pellet region 5 to divide the wafer into pellets. The required number of these registration patterns, the positions to be arranged, and the intervals are determined for each wafer manufacturing process.

However, the size of the pellets has been reduced due to the improvement of the manufacturing technology, and it has become impossible to obtain a space for arranging one set of the registration patterns around one pellet region 5. One pellet region 5 is defined as one cell, and a plurality of cells arranged so as to overlap the scribe lines are virtually regarded as one pellet region (hereinafter, this is referred to as a cell configuration), and a set of matching patterns is provided around the cell region. Has come to be placed.

Therefore, in a drawing apparatus for drawing a pattern on a reticle used at the time of exposure, circuit data after cell formation increases, and processing for converting circuit data to drawing data (hereinafter referred to as EB processing) is performed. The problem of increased time has arisen. Also, the verification time for verifying that the drawing data is equal to the original circuit data has been increased.

[0006]

The first problem is that EB
This means that the processing time increases. The reason is,
This is because the amount of data increases due to the increase in the number of cell components in the pattern data.

The second problem is that the verification time of the drawing data output as a result of the EB processing increases.
The reason is that the data amount increases similarly to the first problem. Since the verification of the drawing data is performed visually by displaying the shape of each process on a screen or the like, if the data amount is doubled, the work time is doubled and the number of steps is increased.

An object of the present invention is to provide a method for designing a pattern of a semiconductor integrated circuit, which can reduce the time required for the EB processing and its verification process.

[0009]

According to the method of designing a pattern of a semiconductor integrated circuit of the present invention, an element pattern for forming a circuit element on a semiconductor wafer by a lithography technique and a semiconductor wafer provided on a scribe line and exposing the semiconductor wafer during exposure. A method for designing a pattern of a semiconductor integrated circuit including a plurality of alignment patterns for determining a position with an apparatus or the like and a dicing pattern used for alignment when a wafer is cut into pellets after forming circuit elements, wherein the dicing pattern , At least one of the plurality of alignment patterns is provided.

In the present invention, two different registration patterns for different purposes are integrally used. For this reason, the area for arranging the alignment pattern is reduced, and there is no need to increase the number of cell configurations to secure the area. If the number of cell configurations is reduced, the total data amount is reduced, and the EB processing for the entire data and the verification time are greatly reduced.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 and 2 are a pattern diagram for explaining a first embodiment of the present invention and a diagram showing a dicing mark integrated with a vernier caliper pattern.

Referring to FIG. 1, the pattern of the semiconductor integrated circuit according to the first embodiment includes a pellet region 5 on which an element pattern for forming circuit elements is formed on a semiconductor wafer by lithography, and a pellet region 5 having the same. A registration pattern and a circuit element comprising a wafer alignment mark 1, a laser stepper alignment mark 2, and a vernier caliper pattern 3 provided on a scribe line 10 surrounding the semiconductor wafer 5 to determine the position of a semiconductor wafer and an exposure apparatus at the time of exposure. A dicing mark 4 used for alignment when the wafer is cut into pellets after the formation is included, and a pattern 6A provided with the vernier caliper pattern 3 is particularly arranged in the dicing mark 4 on the right and lower sides of the scribe line 10. There is a configuration. All of the single dicing marks 4 may be an integrated pattern 6A.

That is, in FIG.
Has a cell configuration in which two are arranged in the X direction and two are arranged in the Y direction. A dicing mark 4 is arranged at each intersection and a corner of the scribe line 10, and another alignment pattern is arranged at the center of the scribe line 10. I have. The vernier caliper pattern 3 of the alignment pattern is integrated with the dicing mark 4 and arranged on the X-axis and the Y-axis of the entire data. This is a caliper pattern 3
Is preferably located on the center line of the reticle,
Since the reticle is formed by repeatedly drawing the pattern data, the reticle is often placed near the intersection of the X axis and the Y axis of the pattern data, and is most easily shared with a dicing mark similarly placed at the intersection of the X axis and the Y axis. That's why.
If the alignment pattern can be sufficiently arranged on the scribe line surrounding one pellet area, there is no need for a cell configuration,
In the case of a small pellet region, it is often too late to form a cell if the cell is not configured at all.

In order to form the dicing mark 6A integrated with the vernier caliper pattern shown in FIG. 2, a portion of the dicing mark 4 overlapping the vernier caliper pattern 3 is hollowed out and the vernier caliper pattern is placed there. Normally, the caliper pattern 3 is smaller than the dicing mark 4, so
As long as the interval specified for each wafer manufacturing process can be maintained, it is possible to place two to three caliper patterns in one dicing mark. Since the dicing mark 4 keeps the original outer shape necessary for cutting the pellet, the accuracy of alignment does not change. Also, since the integrated caliper pattern 3 has the dicing mark 4 hollowed out, the required shape at the time of exposure is secured, and the accuracy does not change.

Note that the cell configuration shown in FIG. 1 is an imposition of pattern data. Since the pattern is formed on the entire reticle by repeating this on an actual reticle, even if the imposition of the pattern data is reduced. The number of exposures for one wafer does not decrease.

FIGS. 3 and 4 are pattern diagrams for explaining the second and third embodiments of the present invention. FIG. 3 shows a pattern 6B in which a dicing mark 4 and a wafer alignment mark 1 are integrated. FIG. 4 shows a pattern 6C in which the dicing mark 4 and the laser stepper alignment mark 2 are integrated. In a place where there is no caliper pattern, if the dicing mark and another matching pattern are used integrally, the area where the matching pattern is arranged is further deleted, and the data amount is reduced.

FIG. 5 is a pattern diagram for explaining a fourth embodiment of the present invention, and shows a pattern 6D in which a wafer alignment mark 1 and a laser stepper alignment mark 2 are arranged in a dicing mark 4.

By arranging two types of alignment marks in the dicing mark in this manner, the area for arranging the alignment pattern is further reduced, and the data amount is also reduced.

Although the case where the wafer alignment mark 1 and the laser stepper alignment mark 2 are arranged in the dicing mark 4 has been described with reference to FIG. 5, it is needless to say that the caliper pattern 3 may be included.

[0020]

The first effect is that the EB processing time is shortened. This shortens the pattern design period. The reason for this is that the use of an integrated registration pattern reduces the number of pattern data cells, thereby reducing the overall data amount.

A second effect is that the verification work of the drawing data after the EB processing is reduced. The reason is that the data amount is reduced as in the first effect.

[Brief description of the drawings]

FIG. 1 is a pattern diagram for explaining a first embodiment of the present invention.

FIG. 2 is a diagram showing a dicing mark integrated with a vernier caliper pattern according to the first embodiment.

FIG. 3 is a diagram showing a dicing mark integrated with a wafer alignment mark according to a second embodiment.

FIG. 4 is a diagram showing a dicing mark integrated with a laser stepper alignment mark according to a third embodiment.

FIG. 5 is a diagram showing a dicing mark integrated with a wafer alignment mark and a laser stepper alignment mark according to a fourth embodiment.

FIG. 6 is a pattern diagram for explaining a conventional technique.

[Description of Signs] 1 Wafer alignment mark 2 Laser stepper alignment mark 3 Vernier caliper pattern 4 Dicing mark 5 Pellet area 6A Dicing mark integrated with vernier caliper pattern 10 Scribe line

Claims (5)

[Claims] 1. An element pattern for forming circuit elements on a semiconductor wafer by lithography, a plurality of alignment patterns provided on scribe lines for determining the position of the semiconductor wafer and the exposure apparatus at the time of exposure, and In a method of designing a pattern of a semiconductor integrated circuit including a dicing pattern used for alignment when a wafer is cut into pellets after forming circuit elements, at least one of the plurality of alignment patterns is provided inside the dicing pattern. A pattern design method for a semiconductor integrated circuit, comprising: 2. A method according to claim 1, wherein the plurality of alignment patterns include a wafer alignment mark for aligning the position of the wafer with the exposure apparatus, a laser stepper alignment mark for aligning the position of the reticle and the wafer, and a pattern of a previous process in each manufacturing process. 2. The pattern design method for a semiconductor integrated circuit according to claim 1, wherein the pattern is a vernier caliper pattern for confirming a position shift. 3. The method according to claim 1, wherein a wafer alignment mark and a laser stepper alignment mark are provided inside the dicing pattern. 4. A dicing pattern provided with a wafer alignment mark and a caliper pattern.
The pattern design method of the semiconductor integrated circuit described in the above. 5. The pattern design method for a semiconductor integrated circuit according to claim 1, wherein the laser stepper alignment mark and the caliper pattern are provided inside the dicing pattern.