JP2006311305A - Passive polyphase filter - Google Patents

Passive polyphase filter Download PDF

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JP2006311305A
JP2006311305A JP2005132558A JP2005132558A JP2006311305A JP 2006311305 A JP2006311305 A JP 2006311305A JP 2005132558 A JP2005132558 A JP 2005132558A JP 2005132558 A JP2005132558 A JP 2005132558A JP 2006311305 A JP2006311305 A JP 2006311305A
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elements
polyphase filter
passive polyphase
input
output
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JP4511410B2 (en
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Masayuki Ozasa
正之 小笹
Akio Yokoyama
明夫 横山
Manabu Okubo
学 大久保
Takao Soramoto
孝夫 空元
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to CN200610077443A priority patent/CN100590967C/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a passive polyphase filter in which components arrangement and a wiring shape are simple and it is easy to uniformize influences by a parasitic element on characteristics. <P>SOLUTION: Four resistive elements R1 to R4, four capacitive elements C1 to C4, four input terminals I1 to I4 for inputting a four-phase signal and four output terminals O1 to O4 for outputting a four-phase signal are provided on one and the same substrate of an integrated circuit. The resistive elements and the capacitative elements are alternately connected so as to have a loop form, and the input terminals and the output terminals are sequentially and alternately connected to each node between the resistive elements and the capacitative elements. The input terminals and the output terminals are collectively arranged in a central area, the four resistive elements are arranged in an area surrounding the input terminals and the output terminals, the four capacitative elements are arranged in an area surrounding the four resistive elements, and the four resistive elements and the four capacitative elements are covered with an upper-layer wiring layer where a uniform conductor layer is formed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、電子機器の信号処理におけるイメージ除去等に使用する受動型ポリフェーズフィルタ(複素フィルタ)に関し、特に構成要素である抵抗、コンデンサおよび入出力端の配置の改良に関する。   The present invention relates to a passive polyphase filter (complex filter) used for image removal or the like in signal processing of an electronic apparatus, and more particularly to improvement in arrangement of resistors, capacitors, and input / output terminals as constituent elements.

電子機器の信号処理におけるイメージ除去に使用する受動型ポリフェーズフィルタは、例えば4相入力の場合、図6に示すような回路構成を有する。この受動型ポリフェーズフィルタは、抵抗R1〜R4、およびコンデンサC1〜C4を、抵抗とコンデンサを交互にループ状に接続して構成されている。I1〜I4は信号を入力する入力端、O1〜O4は信号を出力する出力端である。抵抗R1〜R4は同一の抵抗値、コンデンサC1〜C4は同一の容量値を有する。   A passive polyphase filter used for image removal in signal processing of an electronic device has a circuit configuration as shown in FIG. This passive polyphase filter is configured by connecting resistors R1 to R4 and capacitors C1 to C4 alternately in a loop with resistors and capacitors. I1 to I4 are input terminals for inputting signals, and O1 to O4 are output terminals for outputting signals. The resistors R1 to R4 have the same resistance value, and the capacitors C1 to C4 have the same capacitance value.

図6の回路においては、入力端I1から出力端O1への信号処理として抵抗R1とコンデンサC4で受動型の1次ローパスフィルタが構成され、一方、出力端O2から入力端I1への信号処理としてコンデンサC1と抵抗R1とで受動型の1次ハイパスフィルタが構成される。つまり、入力端I1で本来の入力信号と出力端O2からの信号を合成して出力端O1へ出力する。他の信号入力端からの出力端への信号関係も同様な構成となる。   In the circuit of FIG. 6, as the signal processing from the input terminal I1 to the output terminal O1, a passive first-order low-pass filter is configured by the resistor R1 and the capacitor C4. On the other hand, as the signal processing from the output terminal O2 to the input terminal I1. The capacitor C1 and the resistor R1 constitute a passive primary high-pass filter. That is, the original input signal at the input terminal I1 and the signal from the output terminal O2 are combined and output to the output terminal O1. The signal relationship from the other signal input terminals to the output terminal has the same configuration.

上記構成の受動型ポリフェーズフィルタの集積回路上での配置図(レイアウト)の例を、図7に示す。各参照符号は、図6の回路図に対応させて付されている。この従来の受動型ポリフェーズフィルタの配置では、配線を蛇行させて配線抵抗が等しくなるように配慮されている(例えば、非特許文献1参照。)。   FIG. 7 shows an example of a layout (layout) of the passive polyphase filter having the above configuration on an integrated circuit. Each reference numeral is attached corresponding to the circuit diagram of FIG. In the arrangement of the conventional passive polyphase filter, consideration is given to meandering the wiring so that the wiring resistance becomes equal (see, for example, Non-Patent Document 1).

また、他の従来例の受動型ポリフェーズフィルタの配置図(レイアウト)を、図8に示す(例えば、特許文献1参照。)。この受動型ポリフェーズフィルタの配置では、入力端I1と入力端I4を共用し、入力端I2と入力端I3を共用して、2相入力の場合の集積回路上の配置を実現している。抵抗R1〜R4とコンデンサC1〜C4が90度回転対称であって、抵抗、コンデンサが交互になるように配置され、寄生容量の発生が少なくなるように配慮されている。
IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL.36 NO.6, JUNE 2001, CMOS Mixers and Polyphase Filters for Large Image Rejection, Farbod Behbahani他3名 特開2003−234406号公報(7頁、第1図)
Further, FIG. 8 shows a layout (layout) of another conventional passive polyphase filter (see, for example, Patent Document 1). In the arrangement of the passive polyphase filter, the input terminal I1 and the input terminal I4 are shared, and the input terminal I2 and the input terminal I3 are shared to realize the arrangement on the integrated circuit in the case of two-phase input. The resistors R1 to R4 and the capacitors C1 to C4 are rotationally symmetrical by 90 degrees, and the resistors and the capacitors are arranged alternately so that the occurrence of parasitic capacitance is reduced.
IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL.36 NO.6, JUNE 2001, CMOS Mixers and Polyphase Filters for Large Image Rejection, Farbod Behbahani and 3 others JP 2003-234406 A (page 7, FIG. 1)

従来、電子機器の信号処理のイメージ除去に使用する受動型ポリフェーズフィルタの配置方法においては、集積回路上に実現する場合、複数段の配置を単純にし、その配置から生じる寄生素子による特性への影響を一律にすることが課題であった。   Conventionally, in an arrangement method of a passive polyphase filter used for removing an image of signal processing of an electronic device, when it is realized on an integrated circuit, the arrangement of a plurality of stages is simplified, and characteristics due to parasitic elements resulting from the arrangement are reduced. The challenge was to make the effects uniform.

これに対して、図7に示した4相入力受動型ポリフェーズフィルタの場合、抵抗R1とコンデンサC1を結ぶ配線に対して、抵抗R2とコンデンサC2を結ぶ配線、抵抗R3とコンデンサC3を結ぶ配線、および抵抗R4とコンデンサC4を結ぶ配線による寄生素子である配線抵抗の値を整合させるために、抵抗R2とコンデンサC2を結ぶ配線、抵抗R3とコンデンサC3を結ぶ配線、抵抗R4とコンデンサC4を結ぶ配線を蛇行させている。そのため、受動型ポリフェーズフィルタの配置として複雑な形状となってしまう。   On the other hand, in the case of the four-phase input passive polyphase filter shown in FIG. 7, the wiring connecting the resistor R2 and the capacitor C2 and the wiring connecting the resistor R3 and the capacitor C3 with respect to the wiring connecting the resistor R1 and the capacitor C1. In order to match the value of the wiring resistance which is a parasitic element by the wiring connecting the resistor R4 and the capacitor C4, the wiring connecting the resistor R2 and the capacitor C2, the wiring connecting the resistor R3 and the capacitor C3, and connecting the resistor R4 and the capacitor C4 The wiring is meandering. Therefore, it becomes a complicated shape as arrangement of a passive type polyphase filter.

また、図9に、2段4相入力の受動型ポリフェーズフィルタの回路図を示す。この受動型ポリフェーズフィルタは、抵抗R11〜R14、コンデンサC11〜C14、入力端I11〜I14、および出力端O11〜O14を含む1段目受動型ポリフェーズフィルタと、抵抗R21〜R24、コンデンサC21〜C24、入力端I21〜I24、および出力端O21〜O24を含む2段目受動型ポリフェーズフィルタとを備えている。1段目の出力端O11〜O14が各々、対応する2段目の入力端I21〜I24に接続されている。   FIG. 9 shows a circuit diagram of a passive polyphase filter having two stages and four phases. This passive polyphase filter includes a first-stage passive polyphase filter including resistors R11 to R14, capacitors C11 to C14, input terminals I11 to I14, and output terminals O11 to O14, resistors R21 to R24, and capacitors C21 to C21. And a second-stage passive polyphase filter including C24, input terminals I21 to I24, and output terminals O21 to O24. The first stage output terminals O11 to O14 are respectively connected to the corresponding second stage input terminals I21 to I24.

この受動型ポリフェーズフィルタの集積回路上での配置例として、図7に示した配置方法に基づいて構成した場合の配置図を図10に示す。この配置において、1段目の出力端と2段目の入力端とを接続するためには、抵抗R11とコンデンサC14を結ぶ配線を、1段目の出力O12と2段目の入力I22、出力O13と入力I23、出力O14と入力I24を結ぶ各配線と交差させなければならない。この交差することによる寄生素子である配線容量の値が、フィルタの特性を変化させてしまう。   As an example of the arrangement of the passive polyphase filter on the integrated circuit, an arrangement diagram in the case where the passive polyphase filter is configured based on the arrangement method shown in FIG. 7 is shown in FIG. In this arrangement, in order to connect the output terminal of the first stage and the input terminal of the second stage, the wiring connecting the resistor R11 and the capacitor C14 is connected to the output O12 of the first stage, the input I22 of the second stage, and the output. It must cross each wiring connecting O13 and input I23, and output O14 and input I24. The value of the wiring capacitance, which is a parasitic element due to the intersection, changes the characteristics of the filter.

一方、図8のような4相入力受動型ポリフェーズフィルタの配置においては、抵抗R1と抵抗R3、抵抗R4と抵抗R2の方向が異なるので相対ばらつきが異なり、同一抵抗値が得られ難い。しかも、図9に示した2段4相入力の受動型ポリフェーズフィルタを、図8のような配置方法に基づいて構成すると、図11に示すようにかなり複雑な形状となる。   On the other hand, in the arrangement of the four-phase input passive polyphase filter as shown in FIG. 8, since the directions of the resistors R1 and R3 and the resistors R4 and R2 are different, the relative variations are different and it is difficult to obtain the same resistance value. Moreover, when the passive polyphase filter having two stages and four phases input shown in FIG. 9 is configured based on the arrangement method as shown in FIG. 8, the shape becomes quite complicated as shown in FIG.

本発明は、上記従来の課題を解決するものであり、構成要素の配置および配線の形状が簡潔で、それらの配置から生じる寄生素子による特性への影響を一律にすることが容易であり、更に、複数段に構成した場合でも配置および配線が複雑化することを抑制して、寄生素子による特性への影響を一律にすることが容易な受動型ポリフェーズフィルタを提供することを目的とする。   The present invention solves the above-mentioned conventional problems, and the arrangement of components and the shape of wiring are simple, and it is easy to make uniform the influence on characteristics due to parasitic elements resulting from these arrangements. An object of the present invention is to provide a passive polyphase filter that can easily make the influence on characteristics due to parasitic elements uniform by suppressing complication of arrangement and wiring even when configured in a plurality of stages.

本発明の受動型ポリフェーズフィルタは、基本的な構成として、集積回路の同一基板上に形成された、4個の抵抗素子と、4個の容量素子と、4相の信号を入力するための4個の入力端と、4相の信号を出力するための4個の出力端とを備え、前記抵抗素子と前記容量素子は交互にループ状に接続され、前記抵抗素子と前記容量素子間の各ノードに対して順次、前記入力端および前記出力端が交互に接続される。   The passive polyphase filter of the present invention has a basic configuration for inputting four resistance elements, four capacitance elements, and a four-phase signal formed on the same substrate of an integrated circuit. Four input terminals and four output terminals for outputting a four-phase signal, wherein the resistor element and the capacitor element are alternately connected in a loop, and between the resistor element and the capacitor element The input terminal and the output terminal are alternately connected to each node sequentially.

上記目的を達成するために本発明の第1の構成の受動型ポリフェーズフィルタは、前記入力端および前記出力端は中央領域に集合させて配置され、前記4個の抵抗素子は前記入力端および前記出力端を包囲する領域に配置され、前記4個の容量素子は前記4個の抵抗素子を包囲する領域に配置され、前記4個の抵抗素子および前記4個の容量素子は、均一な導体層が形成された上層の配線層により覆われたことを特徴とする。   To achieve the above object, the passive polyphase filter of the first configuration of the present invention is arranged such that the input end and the output end are gathered in a central region, and the four resistance elements are the input end and The four capacitance elements are arranged in a region surrounding the four resistance elements, and the four resistance elements and the four capacitance elements are uniform conductors. It is characterized by being covered with an upper wiring layer on which the layer is formed.

また、本発明の第2の構成の受動型ポリフェーズフィルタは、前記入力端および前記出力端は中央領域に集合させて配置され、前記4個の容量素子は前記入力端および前記出力端を包囲する領域に配置され、前記4個の抵抗素子は前記4個の容量素子を包囲する領域に配置され、前記4個の抵抗素子および前記4個の容量素子は、均一な導体層が形成された上層の配線層により覆われたことを特徴とする。   In the passive polyphase filter of the second configuration of the present invention, the input end and the output end are arranged in a central area, and the four capacitive elements surround the input end and the output end. The four resistance elements are arranged in a region surrounding the four capacitance elements, and the four resistance elements and the four capacitance elements are formed with a uniform conductor layer. It is characterized by being covered with an upper wiring layer.

上記構成の受動型ポリフェーズフィルタの構成によれば、構成要素である抵抗素子と容量素子の配置、および入出力端との間の配線の構成が簡潔であり、複数段に構成した場合でも配置および配線が複雑化することなく、寄生素子による特性への影響を一律にすることが容易である。   According to the configuration of the passive polyphase filter having the above configuration, the arrangement of the resistive element and the capacitive element, which are the constituent elements, and the configuration of the wiring between the input and output terminals are simple, and the arrangement is made even when configured in multiple stages. In addition, it is easy to uniformize the influence of the parasitic elements on the characteristics without complicating the wiring.

本発明の受動型ポリフェーズフィルタにおいて、前記前記4個の抵抗素子は各々2分割され、分割された各部分抵抗素子が互いに直交する方向に延在するように配置された構成とすることが好ましい。   In the passive polyphase filter according to the present invention, it is preferable that each of the four resistance elements is divided into two, and the divided partial resistance elements are arranged so as to extend in directions orthogonal to each other. .

また、第1、第2のいずれかの構成の受動型ポリフェーズフィルタを複数段備え、前段の前記受動型ポリフェーズフィルタの前記入力端が各々、後段の前記受動型ポリフェーズフィルタの対応する前記出力端に接続された構成とすることができる。   In addition, a plurality of passive polyphase filters having a first or second configuration are provided, and each of the input terminals of the passive polyphase filter in the preceding stage corresponds to the passive polyphase filter in the subsequent stage. It can be configured to be connected to the output end.

以下、本発明の実施の形態について、図面を参照しながら説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(実施の形態1)
図1は、実施の形態1における受動型ポリフェーズフィルタの配置図を示す。この配置は、図6の回路構成を有する4相入力の受動型ポリフェーズフィルタを実現したものである。図7、図8等の従来例と同一の要素については、同一の参照番号を付して説明する。
(Embodiment 1)
FIG. 1 is a layout diagram of a passive polyphase filter according to the first embodiment. This arrangement realizes a four-phase input passive polyphase filter having the circuit configuration of FIG. The same elements as those of the conventional example in FIGS. 7 and 8 will be described with the same reference numerals.

図1の受動型ポリフェーズフィルタは、集積回路の同一基板上に、抵抗値が同一の4個の抵抗R1〜R4と、容量値が同一の4個のコンデンサC1〜C4と、4相の信号を入力するための4個の入力端I1〜I4と、4相の信号を出力するための4個の出力端O1〜O4とを備える。   The passive polyphase filter of FIG. 1 includes four resistors R1 to R4 having the same resistance value, four capacitors C1 to C4 having the same capacitance value, and a four-phase signal on the same substrate of the integrated circuit. 4 input terminals I1 to I4 and four output terminals O1 to O4 for outputting a four-phase signal.

入力端I1〜I4および出力端O1〜O4は、中央領域に集合させて配置されている。本実施の形態では、左側に入力端I1〜I4、右側に出力端O1〜O4が整列される。抵抗R1〜R4は、入力端I1〜I4および出力端O1〜O4を包囲する領域に時計回りに配置される。コンデンサC1〜C4は、抵抗R1〜R4を包囲する領域に時計回りに配置される。更に、抵抗R1〜R4は各々2分割され、部分抵抗R1a、R1b、部分抵抗R2a、R2b、部分抵抗R3a、R3b、部分抵抗R4a、R4bにより形成されている。抵抗R1を形成する部分抵抗R1a、R1bは、互いに直交する方向に延在させて配置される。他の抵抗R2〜R3を形成する部分抵抗も、同様に配置される。   The input terminals I1 to I4 and the output terminals O1 to O4 are arranged in a central area. In the present embodiment, the input terminals I1 to I4 are aligned on the left side, and the output terminals O1 to O4 are aligned on the right side. The resistors R1 to R4 are disposed clockwise in a region surrounding the input terminals I1 to I4 and the output terminals O1 to O4. Capacitors C1 to C4 are arranged clockwise in a region surrounding resistors R1 to R4. Further, each of the resistors R1 to R4 is divided into two and formed by partial resistors R1a and R1b, partial resistors R2a and R2b, partial resistors R3a and R3b, and partial resistors R4a and R4b. The partial resistors R1a and R1b forming the resistor R1 are arranged so as to extend in directions orthogonal to each other. The partial resistors that form the other resistors R2 to R3 are similarly arranged.

抵抗R1〜R4とコンデンサC1〜C4とは、交互にループ状に接続されている。ループ状に接続された抵抗R1〜R4とコンデンサC1〜C4間の各ノードに対して順次、入力端I1、I2、I3、I4、および出力端O2、O3、O4、O1が、交互に接続されている。入力端I1〜I4および出力端O1〜O4と、各ノードとを結ぶ配線1〜8は、配線長が一致するように調整されている。但し、上述のような配置においては、配線1〜8を大きく蛇行させる必要はない。したがって、受動型ポリフェーズフィルタを構成する要素の配置の結果としては、簡単かつ単純な形状となる。   Resistors R1 to R4 and capacitors C1 to C4 are alternately connected in a loop. The input terminals I1, I2, I3, and I4 and the output terminals O2, O3, O4, and O1 are alternately connected to the nodes between the resistors R1 to R4 and the capacitors C1 to C4 connected in a loop. ing. The wirings 1 to 8 connecting the input terminals I1 to I4 and the output terminals O1 to O4 and each node are adjusted so that the wiring lengths match. However, in the arrangement as described above, it is not necessary to greatly meander the wirings 1 to 8. Therefore, the arrangement of the elements constituting the passive polyphase filter results in a simple and simple shape.

図2に、3段4相入力の受動型ポリフェーズフィルタの回路図を示す。この受動型ポリフェーズフィルタは、図9に示した2段4相入力の受動型ポリフェーズフィルタに、抵抗R31〜R34、コンデンサC31〜C34、入力端I31〜I34、および出力端O31〜O34を含む3段目受動型ポリフェーズフィルタを加えたものである。2段目の出力端O21〜O24が各々、対応する3段目の入力端I31〜I34に接続されている。   FIG. 2 shows a circuit diagram of a passive polyphase filter having three stages and four phases. This passive polyphase filter includes resistors R31 to R34, capacitors C31 to C34, input terminals I31 to I34, and output terminals O31 to O34 in addition to the two-stage four-phase input passive polyphase filter shown in FIG. A third-stage passive polyphase filter is added. The second stage output terminals O21 to O24 are connected to the corresponding third stage input terminals I31 to I34, respectively.

この受動型ポリフェーズフィルタを、図1に示した本実施の形態に従って各要素を配置した例を、図3に示す。図3において、1段目受動型ポリフェーズフィルタ9、2段目受動型ポリフェーズフィルタ10、3段目受動型ポリフェーズフィルタ11は、それぞれ図1に示した受動型ポリフェーズフィルタと同様の構成を有する。   FIG. 3 shows an example in which each element of this passive polyphase filter is arranged according to the present embodiment shown in FIG. In FIG. 3, the first-stage passive polyphase filter 9, the second-stage passive polyphase filter 10, and the third-stage passive polyphase filter 11 have the same configuration as the passive polyphase filter shown in FIG. Have

各受動型ポリフェーズフィルタ9〜11を構成する抵抗およびコンデンサは、上層の配線層12により覆われている。配線層12には、均一な導体層が形成されている。更に、配線層12の上層には、1段目受動型ポリフェーズフィルタ9の入力端にそれぞれ接続された入力配線13〜16と、各出力端をそれぞれ対応する各入力端と接続する段間配線17〜20および段間配線21〜24と、3段目受動型ポリフェーズフィルタ11の出力端と接続された出力配線25〜28とが配置されている。   The resistors and capacitors constituting each of the passive polyphase filters 9 to 11 are covered with an upper wiring layer 12. A uniform conductor layer is formed on the wiring layer 12. Further, on the upper layer of the wiring layer 12, input wirings 13 to 16 connected to the input terminals of the first-stage passive polyphase filter 9, and inter-stage wirings connecting the output terminals to the corresponding input terminals, respectively. 17 to 20 and interstage wirings 21 to 24 and output wirings 25 to 28 connected to the output terminals of the third-stage passive polyphase filter 11 are arranged.

受動型ポリフェーズフィルタを構成する4個の抵抗と4個のコンデンサを上層の配線層12で覆うことにより、配線層12と抵抗との間、および配線層12とコンデンサの間には寄生容量が形成される。その発生する寄生容量は、配線層12を交流接地することにより、各抵抗、各コンデンサについて等しい容量値になり、各信号間の位相に同等に作用する。従って、各信号間にフィルタの特性差を生じることはない。また、1段目の出力端と2段目の入力端とを接続する配線には、お互いの配線同士に直接の交差がないので寄生素子である配線容量が生じることはなく、各位相間にフィルタの特性差を生じることはない。さらに、複数段接続しても、前段出力から後段入力への配線長を等しくできるので、各相の寄生抵抗値も一律となり、位相間のフィルタの特性差を生じることはない。段数を更に増加させても同等な効果が得られる。   By covering the four resistors and four capacitors constituting the passive polyphase filter with the upper wiring layer 12, there is a parasitic capacitance between the wiring layer 12 and the resistor and between the wiring layer 12 and the capacitor. It is formed. The parasitic capacitance generated has the same capacitance value for each resistor and each capacitor by AC grounding the wiring layer 12, and acts equally on the phase between the signals. Therefore, there is no difference in filter characteristics between the signals. In addition, the wiring connecting the output terminal of the first stage and the input terminal of the second stage has no direct crossing between the wirings, so that no wiring capacitance as a parasitic element is generated, and a filter is provided between the phases. There is no difference in characteristics. Further, even if a plurality of stages are connected, the wiring length from the preceding stage output to the succeeding stage input can be made equal, so that the parasitic resistance value of each phase is uniform, and there is no difference in filter characteristics between the phases. Even if the number of stages is further increased, the same effect can be obtained.

なお、図1には図示しなかったが、図1における抵抗R1〜R4、およびコンデンサC1〜C4の上層にも、配線層12と同様の配線層が設けられる。また、配線層12の上層には、入力端I1〜I4、出力端O1〜O4に対する外部からの配線が配置される。   Although not shown in FIG. 1, a wiring layer similar to the wiring layer 12 is also provided in the upper layers of the resistors R1 to R4 and the capacitors C1 to C4 in FIG. Further, on the upper layer of the wiring layer 12, wirings from the outside for the input terminals I1 to I4 and the output terminals O1 to O4 are arranged.

以上のように実施の形態1における受動型ポリフェーズフィルタは、入力端および出力端を包囲する領域に4個の抵抗を配置し、4個の抵抗を包囲する領域に4個のコンデンサを配置し、4個の抵抗および4個のコンデンサを上層の配線層により覆った構成を特徴とする。それにより、構成要素の配置を簡潔にし、それら配置から生じる寄生素子による特性への影響が一律にされた、優れた受動型ポリフェーズフィルタを実現することができる。特に、複数段に構成した場合に、要素の配置および配線の複雑化を抑制する効果が大きい。   As described above, in the passive polyphase filter according to the first embodiment, four resistors are arranged in a region surrounding the input end and the output end, and four capacitors are arranged in a region surrounding the four resistors. It is characterized by a configuration in which four resistors and four capacitors are covered with an upper wiring layer. Accordingly, it is possible to realize an excellent passive polyphase filter in which the arrangement of the constituent elements is simplified and the influence of the parasitic elements resulting from the arrangement is uniform on the characteristics. In particular, when configured in a plurality of stages, the effect of suppressing the arrangement of elements and the complexity of wiring is great.

なお、図3に示した複数段の構成においては、抵抗、コンデンサが同一であるものを複数段接続した場合を例として説明したが、要求される特性に応じて各段間で抵抗、コンデンサを異ならせることができる。   In the multi-stage configuration shown in FIG. 3, the case where a plurality of stages having the same resistance and capacitor are connected has been described as an example. Can be different.

また、本実施の形態では3層配線を用いた場合を示したが、抵抗生成層、コンデンサ生成層との寄生容量を低減するために、多層配線により上層の配線を使用することも可能である。   In this embodiment, the case of using the three-layer wiring is shown. However, in order to reduce the parasitic capacitance with the resistance generation layer and the capacitor generation layer, it is also possible to use the upper layer wiring by the multilayer wiring. .

(実施の形態2)
図4は、実施の形態2における受動型ポリフェーズフィルタの配置図を示す。この配置は、図6の回路構成を有する4相入力の受動型ポリフェーズフィルタを実現したものである。図1の実施の形態1と同一の要素については、同一の参照番号を付して説明する。
(Embodiment 2)
FIG. 4 is a layout diagram of the passive polyphase filter according to the second embodiment. This arrangement realizes a four-phase input passive polyphase filter having the circuit configuration of FIG. The same elements as those in the first embodiment in FIG. 1 are described with the same reference numerals.

入力端I1〜I4および出力端O1〜O4は、中央領域に集合させて一列に配置されている。コンデンサC1〜C4は、入力端I1〜I4および出力端O1〜O4を包囲する領域に、反時計回りに配置される。抵抗R1〜R4は、コンデンサC1〜C4を包囲する領域に反時計回りに配置される。   The input terminals I1 to I4 and the output terminals O1 to O4 are arranged in a row in a central area. The capacitors C1 to C4 are arranged counterclockwise in a region surrounding the input terminals I1 to I4 and the output terminals O1 to O4. The resistors R1 to R4 are arranged counterclockwise in a region surrounding the capacitors C1 to C4.

抵抗R1〜R4は、各々2分割された部分抵抗R1a、R1b、部分抵抗R2a、R2b、部分抵抗R3a、R3b、部分抵抗R4a、R4bにより形成されている。抵抗R1を形成する部分抵抗R1a、R1bは、互いに直交する方向に延在させて配置される。他の抵抗R2〜R3を形成する部分抵抗も、同様に配置される。   The resistors R1 to R4 are each formed by partial resistors R1a and R1b, partial resistors R2a and R2b, partial resistors R3a and R3b, and partial resistors R4a and R4b divided into two. The partial resistors R1a and R1b forming the resistor R1 are arranged so as to extend in directions orthogonal to each other. The partial resistors that form the other resistors R2 to R3 are similarly arranged.

入力端I1〜I4および出力端O1〜O4と、抵抗R1〜R4とコンデンサC1〜C4間の各ノードとを結ぶ配線29〜36は、配線長が一致するように調整されている。但し、本実施の形態の配置においては、配線29〜36を大きく蛇行させる必要はない。したがって、受動型ポリフェーズフィルタを構成する要素を配置した結果としては、簡単かつ単純な形状となる。   The wirings 29 to 36 connecting the input terminals I1 to I4 and the output terminals O1 to O4, and the nodes between the resistors R1 to R4 and the capacitors C1 to C4 are adjusted so that the wiring lengths match. However, in the arrangement of the present embodiment, it is not necessary to meander the wirings 29 to 36 greatly. Therefore, as a result of arranging the elements constituting the passive polyphase filter, a simple and simple shape is obtained.

さらに、図2に示した3段4相入力の受動型ポリフェーズフィルタを、図4に示した本実施の形態に従って各要素を配置した例を、図5に示す。図5において、1段目受動型ポリフェーズフィルタ37、2段目受動型ポリフェーズフィルタ38、3段目受動型ポリフェーズフィルタ39は、それぞれ図4に示した受動型ポリフェーズフィルタと同様の構造を有する。   Furthermore, FIG. 5 shows an example in which each element of the three-stage four-phase input passive polyphase filter shown in FIG. 2 is arranged according to the present embodiment shown in FIG. In FIG. 5, the first-stage passive polyphase filter 37, the second-stage passive polyphase filter 38, and the third-stage passive polyphase filter 39 have the same structure as the passive polyphase filter shown in FIG. Have

各受動型ポリフェーズフィルタ37〜39を構成する抵抗およびコンデンサは、上層の均一な導体層が形成された配線層12により覆われている。配線層12の上層には、1段目受動型ポリフェーズフィルタ37の入力端にそれぞれ接続された入力配線40〜43と、各出力端とそれぞれ対応する各入力端とを接続する段間配線44〜47および段間配線48〜51と、3段目受動型ポリフェーズフィルタ39の出力端と接続された出力配線52〜55とが配置されている。   The resistors and capacitors constituting each of the passive polyphase filters 37 to 39 are covered with a wiring layer 12 on which an upper uniform conductor layer is formed. On the upper layer of the wiring layer 12, the input wirings 40 to 43 respectively connected to the input ends of the first-stage passive polyphase filter 37 and the interstage wiring 44 connecting each output end and each corresponding input end. ˜47 and interstage wirings 48 ˜ 51, and output wirings 52 ˜ 55 connected to the output terminals of the third stage passive polyphase filter 39 are arranged.

受動型ポリフェーズフィルタを構成する4個の抵抗と4個のコンデンサを上層の配線層12で覆うことにより、配線層12と抵抗との間、および配線層12とコンデンサの間には寄生容量が形成される。その発生する寄生容量は、配線層12を交流接地することにより、各抵抗、各コンデンサについて等しい容量値になり、各信号間の位相に同等に作用する。従って、各信号間にフィルタの特性差を生じることはない。また、1段目の出力端と2段目の入力端とを接続する配線には、お互いの配線同士に直接の交差がないので寄生素子である配線容量が生じることはなく、各位相間にフィルタの特性差を生じることはない。さらに、複数段接続しても、前段出力から後段入力への配線長を等しくできるので、各相の寄生抵抗値も一律となり、位相間のフィルタの特性差を生じることはない。段数を更に増加させても同等な効果が得られる。   By covering the four resistors and four capacitors constituting the passive polyphase filter with the upper wiring layer 12, there is a parasitic capacitance between the wiring layer 12 and the resistor and between the wiring layer 12 and the capacitor. It is formed. The parasitic capacitance generated has the same capacitance value for each resistor and each capacitor by AC grounding the wiring layer 12, and acts equally on the phase between the signals. Therefore, there is no difference in filter characteristics between the signals. In addition, the wiring connecting the output terminal of the first stage and the input terminal of the second stage has no direct crossing between the wirings, so that no wiring capacitance as a parasitic element is generated, and a filter is provided between the phases. There is no difference in characteristics. Further, even if a plurality of stages are connected, the wiring length from the preceding stage output to the succeeding stage input can be made equal, so that the parasitic resistance value of each phase is uniform, and there is no difference in filter characteristics between the phases. Even if the number of stages is further increased, the same effect can be obtained.

以上のように実施の形態2における受動型ポリフェーズフィルタは、入力端および出力端を包囲する領域に4個のコンデンサを配置し、4個のコンデンサを包囲する領域に4個の抵抗を配置し、4個の抵抗および4個のコンデンサを上層の配線層により覆った構成を特徴とする。それにより、構成要素の配置を簡潔にし、それら配置から生じる寄生素子による特性への影響が一律にされた、優れた受動型ポリフェーズフィルタを実現することができる。また、複数段に構成しても、要素の配置および配線の複雑化が抑制される。   As described above, in the passive polyphase filter according to the second embodiment, four capacitors are arranged in a region surrounding the input end and the output end, and four resistors are arranged in a region surrounding the four capacitors. It is characterized by a configuration in which four resistors and four capacitors are covered with an upper wiring layer. Accordingly, it is possible to realize an excellent passive polyphase filter in which the arrangement of the constituent elements is simplified and the influence of the parasitic elements resulting from the arrangement is uniform on the characteristics. Moreover, even if it is configured in a plurality of stages, the arrangement of elements and the complexity of wiring are suppressed.

なお、図5に示した複数段の構成においては、抵抗、コンデンサが同一であるものを複数段接続した場合を例として説明したが、要求される特性に応じて各段間で抵抗、コンデンサを異ならせることができる。   In the multi-stage configuration shown in FIG. 5, the case where a plurality of stages having the same resistance and capacitor are connected has been described as an example. However, according to the required characteristics, the resistance and capacitor are connected between the stages. Can be different.

また、本実施の形態では3層配線を用いた場合を示したが、抵抗生成層、コンデンサ生成層との寄生容量を低減するために、多層配線により上層の配線を使用することも可能である。   In this embodiment, the case of using the three-layer wiring is shown. However, in order to reduce the parasitic capacitance with the resistance generation layer and the capacitor generation layer, it is also possible to use the upper layer wiring by the multilayer wiring. .

本発明の受動型ポリフェーズフィルタは、要素の配置・配線が簡潔で、フィルタ特性が改善され、電子機器の信号処理、集積回路の設計等として有用である。   The passive polyphase filter of the present invention has simple arrangement and wiring of elements, improved filter characteristics, and is useful for signal processing of electronic equipment, design of integrated circuits, and the like.

実施の形態1における4相入力の受動型ポリフェーズフィルタの配置図Arrangement diagram of 4-phase input passive polyphase filter in Embodiment 1 3段4相入力受動型ポリフェーズフィルタの回路図Circuit diagram of 3-stage 4-phase input passive polyphase filter 実施の形態1における3段4相入力の受動型ポリフェーズフィルタの配置図Arrangement of 3-stage 4-phase input passive polyphase filter in the first embodiment 実施の形態2における4相入力の受動型ポリフェーズフィルタの配置図Arrangement diagram of 4-phase input passive polyphase filter in embodiment 2 実施の形態2における3段4相入力の受動型ポリフェーズフィルタの配置図Arrangement of 3-stage 4-phase input passive polyphase filter in Embodiment 2 4相入力の受動型ポリフェーズフィルタの回路図Circuit diagram of 4-phase input passive polyphase filter 従来例における4相入力の受動型ポリフェーズフィルタの配置図Arrangement of four-phase input passive polyphase filter in the conventional example 他の従来例における4相入力の受動型ポリフェーズフィルタの配置図Arrangement of four-phase input passive polyphase filter in another conventional example 2段4相入力の受動型ポリフェーズフィルタの回路図Circuit diagram of passive polyphase filter with two-stage four-phase input 従来例における2段4相入力の受動型ポリフェーズフィルタの配置図Arrangement of two-stage four-phase input passive polyphase filter in the conventional example 他の従来例における2段4相入力の受動型ポリフェーズフィルタの配置図Arrangement of two-stage four-phase input passive polyphase filter in another conventional example

符号の説明Explanation of symbols

1〜8、29〜36 配線
9、37 1段目受動型ポリフェーズフィルタ
10、38 2段目受動型ポリフェーズフィルタ
11、39 3段目受動型ポリフェーズフィルタ
12 配線層
13〜16、40〜43 入力配線
17〜24、44〜51 段間配線
25〜28、52〜55 出力配線
C1〜C4、C11〜C14、C21〜C24、C31〜C34 コンデンサ
I1〜I5、I11〜I14、I21〜I24、I31〜I34 入力端
O1〜O4、O11〜O14、O21〜O24、O31〜O34 出力端
R1〜R4、R11〜R14、R21〜R24、R31〜R34 抵抗
R1a、R1b、R2a、R2b、R3a、R3b、R4a、R4b 部分抵抗

1-8, 29-36 Wiring 9, 37 First-stage passive polyphase filter 10, 38 Second-stage passive polyphase filter 11, 39 Third-stage passive polyphase filter 12 Wiring layers 13-16, 40- 43 Input wiring 17-24, 44-51 Interstage wiring 25-28, 52-55 Output wiring C1-C4, C11-C14, C21-C24, C31-C34 Capacitors I1-I5, I11-I14, I21-I24, I31 to I34 Input terminals O1 to O4, O11 to O14, O21 to O24, O31 to O34 Output terminals R1 to R4, R11 to R14, R21 to R24, R31 to R34 Resistors R1a, R1b, R2a, R2b, R3a, R3b, R4a, R4b Partial resistance

Claims (6)

集積回路の同一基板上に形成された、4個の抵抗素子と、4個の容量素子と、4相の信号を入力するための4個の入力端と、4相の信号を出力するための4個の出力端とを備え、前記抵抗素子と前記容量素子は交互にループ状に接続され、前記抵抗素子と前記容量素子間の各ノードに対して順次、前記入力端および前記出力端が交互に接続された受動型ポリフェーズフィルタにおいて、
前記入力端および前記出力端は中央領域に集合させて配置され、前記4個の抵抗素子は前記入力端および前記出力端を包囲する領域に配置され、前記4個の容量素子は前記4個の抵抗素子を包囲する領域に配置され、前記4個の抵抗素子および前記4個の容量素子は、均一な導体層が形成された上層の配線層により覆われたことを特徴とする受動型ポリフェーズフィルタ。
Four resistor elements, four capacitor elements, four input terminals for inputting a four-phase signal, and four-phase signal output formed on the same substrate of the integrated circuit Four output terminals, and the resistance element and the capacitive element are alternately connected in a loop, and the input terminal and the output terminal are alternately arranged for each node between the resistive element and the capacitive element. In the passive polyphase filter connected to
The input end and the output end are arranged in a central region, the four resistance elements are arranged in a region surrounding the input end and the output end, and the four capacitance elements are the four capacitance elements. A passive polyphase, wherein the four resistive elements and the four capacitive elements are disposed in a region surrounding the resistive element, and are covered with an upper wiring layer on which a uniform conductor layer is formed. filter.
集積回路の同一基板上に形成された、4個の抵抗素子と、4個の容量素子と、4相の信号を入力するための4個の入力端と、4相の信号を出力するための4個の出力端とを備え、前記抵抗素子と前記容量素子は交互にループ状に接続され、前記抵抗素子と前記容量素子間の各ノードに対して順次、前記入力端および前記出力端が交互に接続された受動型ポリフェーズフィルタにおいて、
前記入力端および前記出力端は中央領域に集合させて配置され、前記4個の容量素子は前記入力端および前記出力端を包囲する領域に配置され、前記4個の抵抗素子は前記4個の容量素子を包囲する領域に配置され、前記4個の抵抗素子および前記4個の容量素子は、均一な導体層が形成された上層の配線層により覆われたことを特徴とする受動型ポリフェーズフィルタ。
Four resistor elements, four capacitor elements, four input terminals for inputting a four-phase signal, and four-phase signal output formed on the same substrate of the integrated circuit Four output terminals, and the resistance element and the capacitive element are alternately connected in a loop, and the input terminal and the output terminal are alternately arranged for each node between the resistive element and the capacitive element. In the passive polyphase filter connected to
The input end and the output end are arranged in a central area, the four capacitive elements are arranged in a region surrounding the input end and the output end, and the four resistance elements are the four resistance elements. A passive polyphase, wherein the four resistive elements and the four capacitive elements are disposed in a region surrounding the capacitive element, and are covered with an upper wiring layer on which a uniform conductor layer is formed. filter.
前記前記4個の抵抗素子は各々2分割され、分割された各部分抵抗素子が互いに直交する方向に延在するように配置された請求項1または2に記載の受動型ポリフェーズフィルタ。   3. The passive polyphase filter according to claim 1, wherein each of the four resistance elements is divided into two, and the divided partial resistance elements are arranged to extend in directions orthogonal to each other. 請求項1〜3のいずれか1項に記載の受動型ポリフェーズフィルタを複数段備え、前段の前記受動型ポリフェーズフィルタの前記入力端が各々、後段の前記受動型ポリフェーズフィルタの対応する前記出力端に接続された受動型ポリフェーズフィルタ。   A plurality of the passive polyphase filters according to any one of claims 1 to 3, wherein the input terminals of the passive polyphase filter at the front stage correspond to the passive polyphase filter at the rear stage. A passive polyphase filter connected to the output end. 請求項1〜4のいずれか1項に記載の受動型ポリフェーズフィルタを備えた集積回路。   An integrated circuit comprising the passive polyphase filter according to claim 1. 請求項5に記載の集積回路を備えた受信機。

A receiver comprising the integrated circuit according to claim 5.

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