JP2008306007A - Inductor, wiring board, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compact on-chip inductor which has low parasitic resistance even in a high frequency range and whose characteristics are symmetrical when the inductor is viewed from an input/output terminal. <P>SOLUTION: Provided are an even number of inductor elements L1 and L2 extending spirally from input terminal IN1 and IN2 to output terminals OUT1 and OUT2 over a plurality of layers having an insulating layer interposed. The inductor elements L1 and L2 are disposed generating magnetic fields in the same direction, and also connected in parallel so that inductor characteristics including a Q value which are viewed from the input terminals are nearly the same as those which are viewed from the output terminals. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an on-chip type inductor used as one of passive components in a chip type semiconductor device having an active component and a passive component, and a chip type semiconductor device having such an inductor.

  In recent years, various high-speed digital wireless systems such as wireless LAN, Bluetooth (trademark or registered trademark), and digital terrestrial television broadcasting have been put into practical use. The wireless circuit is often constituted by a chip-type semiconductor device. This type of semiconductor device has an on-chip inductor as a passive component. This inductor has a spiral inductor element formed on a semiconductor substrate. Although the inductance of the on-chip type inductor is at most several nH, it is a practical inductance for a radio circuit operating in the GHz band.

  In this type of inductor, a wiring length of several mm is necessary to realize an inductance of several nH. However, this length is longer than other wirings formed on the semiconductor substrate. For this reason, a large parasitic resistance is generated, and the circuit performance is degraded. Further, the Q value as an index of performance of the inductor is lowered due to parasitic resistance. For this reason, it is desirable that the parasitic resistance is small also in this respect.

  As shown in FIGS. 1A and 1B, a planar inductor, which is one of this type of inductor, has a single-layer inductor element. As shown in FIG. 1A, the inductor element L has a spiral shape, thereby realizing a wiring length of several mm. Referring to FIG. 1B, the inductor element L has a cross-sectional structure that is wider than the thickness in order to reduce the series parasitic resistance of the inductor element. However, an inductor with a length of several mm cannot be said to have a sufficiently low parasitic resistance. For example, when formed of a general wiring material that can be formed on a semiconductor substrate, such an inductor has a resistance value of several Ω to several tens of Ω. In FIG. 1B, the symbol IS indicates an insulating layer.

  As a measure for reducing the parasitic resistance, Non-Patent Document 1 discloses a multi-layer series connection type inductor. This inductor has a plurality of layers of inductor elements, and these inductor elements are connected in parallel. Referring to FIG. 2, in the multi-layer series connection type inductor, the inductor element pieces L11, L12, and L13 have similar shapes to each other and are not shown in FIG. In addition, it is arranged over three layers through the insulating layer IS. The inductor element pieces L11, L12, and L13 are connected in parallel to each other through vias P1 and P2. Therefore, a signal input from the common input terminal IN is output from the common output terminal OUT through the inductor element pieces L11, L12, and L13 connected in parallel. In a multilayer serial connection type inductor, since a plurality of inductor elements are connected in parallel, the resistance value is reduced as compared with the case where the inductor is formed by one wiring layer.

  On the other hand, Patent Document 1 proposes a multilayer series connection type inductor. This inductor has a plurality of layers of inductor elements, and these inductor elements are connected in series. Referring to FIG. 3, in the multi-layer series connection type inductor, the inductor element pieces L11, L12, and L13 have similar shapes to each other through the insulating layer IS in a direction without deviation with respect to the center point X. It is arranged over three layers. That is, the inductor element piece L11 goes around the layer indicated by the solid line. The inductor element piece L12 goes around the middle layer represented by a rough broken line. The inductor element piece L13 goes around the lower layer represented by a dense broken line. The inductor element pieces L11, L12, and L13 are connected in series with each other via vias A and B. Therefore, a signal that enters from the terminal IN formed at one end of the inductor element piece L11 passes through the inductor element pieces L11, L12, and L13 connected in series and from the terminal OUT formed at one end of the inductor element piece L13. Is output. The multilayer serial connection type inductor has a small effect of the skin effect because the effective thickness of the wiring layer is small. Furthermore, since the inductor element pieces are connected in series, the current values flowing through them are equal. Therefore, the increase in series resistance due to the skin effect is small compared to the multilayer series connection type inductor.

  In addition, when copper (Cu) is used as the wiring material, it is difficult to make a wide wiring width due to the manufacturing process. FIGS. 4A and 4B show examples of inductor structures that can avoid such a wiring width limitation. Referring to FIGS. 4A and 4B, the inductor element L ′ makes two turns on the insulating layer IS in the same manner as the inductor element L shown in FIGS. 1A and 1B. However, the wiring width of the inductor element L ′ is wider than that of the inductor element L shown in FIGS. This is because the inductor element L 'is not a simple flat plate but has a plurality of slits S extending intermittently about ¼ around the winding direction. By providing the inductor element with the slits in this way, even if the wiring material is copper, it is possible to realize a wiring width wider than the wiring width that is normally possible.

JP 2001-351980 A IEEE Electron Devices, Vol.51, No.3, Mar. 2004, pp460-466 IEEE Electron Device Letters, Vol.25, No.11, Nov. 2004, pp722-724

  However, in the multilayer series connection type inductor, when this inductor is used in the GHz band, the series resistance rises due to the skin effect. Since the skin depth is several μm when the inductor is used at 1 GHz, it is about the same as the width and thickness of the wiring on the semiconductor substrate, and the influence cannot be ignored. In particular, in the connection structure as shown in FIGS. 2A and 2B, since the effective film thickness of the wiring can be regarded as increasing, the influence of the skin effect is large. Thus, for example, Non-Patent Document 2 reports that even if the series resistance is low in the low frequency band, the series resistance reduction effect as low as the low frequency band cannot be exhibited in the GHz band.

  In addition, the multi-layer series connection type inductor has a problem that the characteristics when the inductor is viewed from both terminals are asymmetric because the inductor element pieces (wiring layers) provided with the terminals at both ends of the inductor are different.

  In addition, when copper (Cu) is used as the wiring material, in the structure in which the slit is provided in order to realize a wiring width wider than the normal wiring width, an extra area occupied by the slit is required. This hinders downsizing of on-chip inductors and chip-type semiconductor devices having such inductors.

  Therefore, an object of the present invention is to provide a small on-chip type inductor having a low parasitic resistance even in a high-frequency band and having a symmetrical characteristic when viewed from the input / output terminal.

  According to the present invention, on-chip type inductors used in a chip type semiconductor device, each including an even number of inductors that spirally extend from an input terminal to an output terminal across a plurality of layers via an insulating layer The even number of inductor elements are arranged so that the generated magnetic fields are in the same direction, and the inductor characteristic including the Q value viewed from the input terminal and the one viewed from the output terminal are An inductor characterized by being connected in parallel so as to be substantially the same can be obtained.

  According to the present invention, the even number of inductor elements are substantially congruent with each other in a plan view, and are arranged without substantially deviating from each other in the rotation direction with respect to a common center point. Half of the inductor elements, the input terminal is in the uppermost layer of the plurality of layers, the output terminal is in the lowermost layer, and the remaining half of the even number of inductor elements The inductor element has the input terminal at the lowermost layer of the plurality of layers, the output terminal at the uppermost layer, and the input terminals of the even number of inductor elements are connected to each other. And an inductor in which the output terminals are connected to each other.

  Each of the even number of inductor elements is composed of a plurality of inductor element pieces sequentially connected in series from the input terminal to the output terminal, and the plurality of inductor element pieces each circulate in each of the plurality of layers. Inductor element pieces that are adjacently connected in series may be connected to each other via vias.

  The inductor element pieces in the second layer, which is lower than the first layer of the plurality of layers, have a congruent shape in plan view and are arranged without deviation in the rotation direction with respect to the common center point. The additional inductor element piece is provided in a third layer which is lower than the second layer, and the additional inductor element piece is parallel to the inductor element piece in the second layer through a via. It may be connected.

  The inductor element piece in the second layer that is lower than the first layer of the plurality of layers may be wider than the inductor element piece in the first layer.

  Of the even number of inductor elements, the inductor element on the outer periphery may be wider than the inductor element on the inner periphery at least in part.

  In addition, according to the present invention, it includes a plurality of wiring layers stacked via an insulating layer and the inductor, and the inductor element is configured using any two or more of the plurality of wiring layers. A wiring board characterized by the above can be obtained.

  Furthermore, according to the present invention, there is provided a chip-type semiconductor device comprising a wiring board, an active component mounted on the wiring board, and the inductor as a passive component mounted on the wiring board. can get.

  In addition, according to the present invention, an oscillation circuit having the inductor and a capacitor having a fixed or variable capacitance value connected in parallel or in series to the inductor can be obtained.

  According to the present invention, there is also provided an on-chip type inductor for use in a chip type semiconductor device, wherein an even number of spirals extending from an input terminal to an output terminal in a spiral manner over a plurality of layers via an insulating layer. The even number of inductor elements are substantially congruent to each other in a plan view, and are arranged without substantially deviating from each other in the rotation direction with respect to a common center point. Half of the inductor elements are such that the input terminal is on the top layer of the plurality of layers and the output terminal is on the bottom layer, and the other half of the even number of inductor elements is the inductor The element has the input terminal in the lowermost layer of the plurality of layers, the output terminal in the uppermost layer, and each of the even number of inductor elements. With complete power terminals are connected to each other, the inductor and the output terminal is equal to or connected to each other is obtained.

  The inductor according to the present invention has a low parasitic resistance even in a high frequency band, has a symmetrical inductor characteristic when viewed from the input / output terminal, and is small.

  The inductor according to the present invention has an even number of inductor elements extending spirally from the input terminal to the output terminal over a plurality of layers via the insulating layer. The even number of inductor elements are arranged so that the generated magnetic fields are in the same direction, and the inductor characteristics including the Q value viewed from the input terminal are substantially the same as those viewed from the output terminal. Connected in parallel.

  More specifically, in the inductor according to the present invention, the even number of inductor elements have a substantially congruent shape in plan view, and are arranged substantially without mutual displacement in the rotation direction with respect to a common center point. Half of the even number of inductor elements have their input terminals on the top layer of the plurality of layers and their output terminals on the bottom layer. The remaining half of the even number of inductor elements have their input terminals at the bottom layer of the plurality of layers and their output terminals at the top layer. The input terminals of the even number of inductor elements are connected to each other, and the output terminals are connected to each other.

  Thereby, the symmetry of the inductor characteristic including the Q value is improved while realizing the high inductance and the low series resistance similar to the multilayer series connection. Furthermore, the increase in the occupied area can be eliminated by matching the upper limit of the wiring width of the present invention with the limitation of the wiring width peculiar to the Cu wiring.

  Embodiments of the present invention will be described below with reference to the drawings.

  Referring to FIG. 5A, the inductor according to the first embodiment of the present invention is an on-chip type inductor used in a chip type semiconductor device. This inductor has two inductor elements L1 and L2. The inductor element L1 extends in a spiral shape from the input terminal IN1 to the output terminal OUT1 over three layers via an insulating layer. The inductor element L2 also extends spirally from the input terminal IN2 to the output terminal OUT2 over three layers with an insulating layer interposed therebetween.

  In the present embodiment, the inductor element extends over three layers. However, in the present invention, the inductance element only needs to extend over a plurality of layers, and may extend over two layers or four layers or more.

  The inductor elements L1 and L2 are arranged so that the generated magnetic fields are in the same direction, and the inductor characteristics including the Q value viewed from the input terminal are substantially the same as those viewed from the output terminal. Connected in parallel.

  More specifically, the inductor element L1 and the inductor element L2 have substantially the same shape in plan view, and are disposed substantially without mutual displacement in the rotation direction with respect to the common center point X. The inductor element L1 has an input terminal IN1 in the uppermost layer of the three layers and an output terminal OUT1 in the lowermost layer. On the other hand, the inductor element L2 has an input terminal IN2 in the lowermost layer of the plurality of layers and an output terminal OUT2 in the uppermost layer.

  Although not shown in FIG. 5 (a), the input terminal IN1 of the inductor element L1 and the input terminal IN2 of the inductor element L2 are connected to each other as shown in FIG. 5 (b). Further, the output terminal OUT1 of the inductor element L1 and the output terminal OUT2 of the inductor element L2 are also connected to each other as shown in FIG. Therefore, the inductor elements L1 and L2 are connected in parallel.

  The inductor element L1 includes inductor element pieces L11, L12, and L13 that are sequentially connected in series from the input terminal IN1 to the output terminal OUT1. Inductor element pieces L11, L12, and L13 each circulate once in three layers, and adjacent inductor element pieces connected in series are connected to each other via vias A1 and B1. The inductor element L2 includes inductor element pieces L21, L22, and L23 that are sequentially connected in series from the input terminal IN2 to the output terminal OUT2. The inductor element pieces L21, L22, and L13 each circulate once in the three layers, and adjacent inductor element pieces connected in series are connected to each other via vias A2 and B2.

  That is, the inductor element piece L11 goes around the outer periphery of the upper layer represented by the solid line from the terminal IN1. The inductor element piece L12 is connected to the inductor element piece L11 via the via A1 and goes around the outer periphery of the middle layer indicated by a rough broken line. The inductor element piece L13 is connected to the inductor element piece L12 via the via B1, and goes around the outer periphery of the lower layer indicated by a dense broken line to the terminal OUT1. Therefore, the signal input from the terminal IN1 is output from the terminal OUT1 through the inductor element pieces L11, L12, and L13. On the other hand, the inductor element piece L21 goes around the inner circumference of the lower layer represented by a dense broken line from the terminal IN2 which is not displaced with respect to the common center point X with respect to the terminal IN1. The inductor element piece L22 is connected to the inductor element piece L11 via the via A2, and makes a round around the outer periphery of the middle layer represented by a rough broken line. The inductor element piece L13 is connected to the inductor element piece L22 via the via B2, and goes around the outer periphery of the upper layer indicated by the solid line to the terminal OUT2. Therefore, the signal input from the terminal IN2 is output from the terminal OUT2 through the inductor element pieces L21, L22, and L23.

  In FIG. 5 (a), there is a relatively wide space between the outer inductor element L1 and the inner inductor element L2. This is because FIG. 5 (a) is a conceptual diagram. It is. Actually, only a minimum interval is provided between the outer inductor element L1 and the inner inductor element L2.

  Further, in the present invention, the term “substantially congruent in plan view” includes a relationship such as the outer peripheral inductor element L1 and the inner peripheral inductor L2 with a minimum interval as in the present embodiment.

  Now, the signal passing through the inductor element L1 and the signal passing through the inductor element L2 have the same direction. Therefore, the magnetic field generated by the inductor element L1 and the magnetic field generated by the inductor element L2 are in phase, and both magnetic fields strengthen each other. Therefore, the total inductance is (L0 + M) / 2 when the self-inductance of the inductor element L1 and the inductor element L2 is both L0 and the mutual inductance of both is M. And since the inductor element L1 and the inductor element L2 are symmetrical shapes, both inductance is equal to each other. Therefore, when the inductor element L1 and the inductor element L2 are arranged close to each other as in the present invention, the mutual inductance M is substantially equal to L0. As a result, the inductance of the inductor according to the present embodiment is substantially equal to the self-inductance L0 of one inductor element.

  The inductor according to the second embodiment of the present invention is characterized in that it has an additional inductor element piece.

  Referring to FIG. 6, the on-chip type inductor according to the second embodiment of the present invention has two inductor elements L1 and L2. The inductor element L1 extends spirally from an input terminal (not shown) to an output terminal over two layers through the insulating layer IS. The inductor element L2 also extends spirally from an input terminal (not shown) to the output terminal over two layers through the insulating layer IS. The inductor elements L1 and L2 are arranged so that the generated magnetic fields are in the same direction, and the inductor characteristics including the Q value viewed from the input terminal are substantially the same as those viewed from the output terminal. Connected in parallel.

  More specifically, although the inductor element L1 and the inductor element L2 are not shown in FIG. 6, they have substantially the same shape in plan view, and are mutually in the rotational direction with respect to a common center point (not shown). It is arranged almost without deviation. The inductor element L1 has an input terminal in the uppermost layer of the two layers and an output terminal in the lowermost layer (in this example, the middle layer). On the other hand, the inductor element L2 has an input terminal at the lowermost layer of the plurality of layers and an output terminal at the uppermost layer. Further, although not shown in FIG. 6, the input terminal of the inductor element L1 and the input terminal of the inductor element L2 are connected to each other. The output terminal of the inductor element L1 and the output terminal of the inductor element L2 are also connected to each other. Therefore, the inductor elements L1 and L2 are connected in parallel. The inductor element L2 includes inductor element pieces L21 and L22 that are sequentially connected in series from the input terminal to the output terminal. Similarly, the inductor element L1 includes inductor element pieces L11 and L12 that are sequentially connected in series from the input terminal to the output terminal. Each inductor element piece makes one turn in each layer, and adjacent inductor element pieces connected in series are connected to each other via vias (not shown).

  Referring to FIG. 6, the inductor is a third lower layer than the second layer (in this example, the middle layer) which is lower than the first layer (in this example, the upper layer) of the plurality of layers. And additional inductor element pieces L12 ′ and L21 ′ formed in the lower layer (in this example, the lower layer). Although the additional inductor element pieces L12 ′ and L21 ′ are not shown in FIG. 6 with respect to the inductor element pieces L12 and L21 in the second layer, they have a congruent shape in plan view and a common center point (see FIG. (Not shown) is arranged without deviation in the rotation direction.

  The additional inductor element piece L12 'is connected in parallel to the inductor element piece L12 via a via. Similarly, the additional inductor element piece L21 'is also connected in parallel to the inductor element piece L21 via the via P. Here, the pair of the inductor element piece L12 and the additional inductor element piece L12 'connected to each other by the via P can be regarded as one inductor element piece. Similarly, a pair of the inductor element piece L21 and the additional inductor element piece L21 'connected to each other by vias can also be regarded as one inductor element piece.

  In the present embodiment, an additional wiring (additional inductor element piece) is connected in parallel via a via to the wiring (inductor element piece) of the inductor formed in the lower layer (in this embodiment, the middle layer). . A pair of wiring and additional wiring connected in parallel can be regarded as a single wiring having an increased thickness. As a result, even a lower-layer wiring having a small thickness can obtain a substantially large cross-sectional area, thereby realizing a low wiring resistance.

  Next, the function and effect of the present invention will be described.

  Next, assuming a chip-type semiconductor device having a multilayer wiring board of a 90-nm generation six-layer Cu (copper) wiring process, an on-chip inductor according to the present invention and a multilayer serial connection type on-state as a comparative example The characteristics of a chip type inductor and a multilayer series connection type on-chip type inductor are compared.

  In the Cu wiring process, an Al (aluminum) wiring layer for performing wire bonding is added to the upper layer of the Cu wiring layer. For this reason, the total number of wiring layers is seven. In a multilayer wiring layer structure, the film thickness of each layer varies depending on the layer, and in particular, the upper wiring layer has a larger film thickness. Since the series parasitic resistance is smaller as the film thickness is larger, the upper wiring layer is more suitable for configuring the inductor element. Therefore, consider a case where an inductor is configured by using five layers of the third to sixth Cu wiring layers M3 to M6 and the Al wiring layer PAD. In general, the Cu wiring layers M3 to M5 are thinner than the upper Cu wiring layer M6 and the Al wiring layer PAD. For this reason, in the following verification, in any of the inductors, the Cu wiring layers M3 to M5 are connected in parallel to form an integrated Cu wiring layer M35.

  Referring to FIGS. 7A to 7C, in the on-chip type inductor according to the present invention, the inductor elements L1 and L2 are respectively connected to the Al wiring layer PAD, the Cu wiring layer M6, and the Cu wiring layer M35 through vias. Extending around the center of the three layers. Each of the inductor elements L1 and L2 has a width (wiring width) of 10 μm. The inner diameter of the inductor element L2 on the inner periphery is 40 μm. The outer shape of the inductor (the outer diameter of the inductor element L1) is 85 μm.

  Referring to FIGS. 8A to 8C, an inductor element L in which additional inductor elements L ′ and L ″ are connected in parallel via a via P in a multilayer serial connection type on-chip type inductor as a comparative example. The width (wiring width) of the inductor element L is 10 μm, the inner diameter of the inductor element L is 30 μm, and the outer shape of the inductor (the outer diameter of the inductor element L) is 100 μm. is there.

  Referring to FIGS. 9A to 9C, in another on-chip type multilayer connection type on-chip inductor as a comparative example, the inductor element LL includes an Al wiring layer PAD and a Cu wiring layer M6 through vias. , And the Cu wiring layer M35, and each of the three layers makes one turn. The width (wiring width) of the inductor element LL is 20 μm. The inner diameter of the inductor element LL is 40 μm. The outer shape of this inductor (the outer diameter of the inductor element LL) is 85 μm.

  When the Cu wiring process is used, the maximum wiring width that can be manufactured is about 10 μm. For this reason, in the multilayer parallel connection as a comparative example, it is necessary to form the slit SL in the inductor element LL (wiring) having a width of 20 μm so that the wiring width is 10 μm or less as shown in FIG. On the other hand, in the present invention, each of the inductor elements L1 and L2 has a wiring width of 10 μm, and is suppressed to a wiring width that can be manufactured using a Cu wiring process. The cross-sectional shape of the present invention in FIG. 7C is almost the same as the cross-sectional shape of the multilayer parallel connection in FIG. In a situation where the wiring width needs to be 10 μm or less for the convenience of the Cu wiring process, when arranging a plurality of inductor elements in parallel for the purpose of realizing a high inductance value, a gap is provided between the inductor elements. This necessitates an increase in the area occupied by the inductor. However, in the present invention, the occupied area can be suppressed to be the same as that of the inductor wiring in which the slit is formed.

  Next, these three on-chip inductors were simulated using a three-dimensional electromagnetic simulator and the characteristics were compared. The parameters to be compared correspond to elements in the simple LCR equivalent diagram shown in FIG. In FIG. 10, the terminal on the capacitor C1 side corresponds to the terminal IN, and the terminal on the capacitor C2 side corresponds to the terminal OUT. L0 is a series inductance, R0 is a series resistance, C1 and C2 are wiring parasitic capacitances, and R1 and R2 are substrate resistances.

  11 shows the inductor of the present invention shown in FIGS. 7A to 7C, the multilayer series connection type inductor shown in FIGS. 8A to 8C, and FIGS. The inductance of the multilayer series connection system shown in c) is shown. As shown in FIG. 11, the inductances of the present invention and the two comparative examples are substantially equal.

  FIG. 12 shows the Q values of the inductors of the present invention and two comparative examples. As the Q value, the Q value viewed from the input terminal IN side with the output terminal OUT side connected to the ground, and the Q value viewed from the output terminal OUT side with the input terminal IN side connected to the ground. Both are shown. As shown in FIG. 12, the Q value of the inductor of the present invention is higher than that of the multilayer series connection type inductor. In addition, Q values observed from the input terminal IN side and the output terminal OUT side of the multilayer series connection type inductor are greatly different. On the other hand, in this invention, it turns out that there is no difference in both and the symmetry is excellent. Also, a better Q value is obtained than the inferior Q value of the multilayer series connection type inductor.

  FIG. 13 shows the parasitic capacitance C2 as viewed from the input terminal IN side C1 and the output terminal OUT side in the inductors of the present invention and two comparative examples. A multi-layer series connection type inductor has a large difference in parasitic capacitance between the input terminal IN side and the output terminal OUT side. In contrast, in the present invention, it can be seen that the difference in parasitic capacitance between the input terminal IN side and the output terminal OUT side is small.

  FIG. 14 shows the series parasitic resistance in the inductor of the present invention and two comparative examples. The series parasitic resistance of the inductor according to the present invention is substantially the same as that of a multilayer series connection type inductor, and is smaller than that of a multilayer series connection type inductor, particularly in a high frequency band. This is because the inductor according to the present invention can reduce the influence of the skin effect, similarly to the multilayer serial connection type inductor.

  The inductor according to the third embodiment of the present invention is characterized in that it has four inductor elements.

  Referring to FIGS. 15A and 15B, the on-chip inductor according to the third embodiment of the present invention has four inductor elements L1 to L4. The inductor element L1 extends in a spiral shape from the input terminal IN1 to the output terminal OUT1 over three layers via an insulating layer. The inductor element L2 also extends spirally from the input terminal IN2 to the output terminal OUT2 over three layers with an insulating layer interposed therebetween. The inductor element L3 also extends spirally from the input terminal IN3 to the output terminal OUT3 over three layers with an insulating layer interposed therebetween. The inductor element L4 also extends spirally from the input terminal IN4 to the output terminal OUT4 over three layers through the insulating layer. The inductor elements L1 to L4 are arranged so that the generated magnetic fields are in the same direction, and the inductor characteristics including the Q value viewed from the input terminal are substantially the same as those viewed from the output terminal. Connected in parallel.

  More specifically, the inductor elements L <b> 1 to L <b> 4 have substantially the same shape in plan view, and are arranged substantially without mutual displacement in the rotation direction with respect to the common center point X.

  The inductor elements L1 and L3, which are half of the four inductor elements, have input terminals IN1 and IN3 in the top layer of the three layers, and output terminals OUT1 and OUT3 in the bottom layer. On the other hand, the inductor elements L2 and L4, which are the other half of the four inductor elements, have their input terminals IN2 and IN4 in the lowest layer of the plurality of layers and their output terminals OUT2 and OUT4 in the uppermost layer. .

  Further, although not shown in FIG. 15A, the input terminals IN1 to IN4 of the inductor elements L1 to L4 are connected to each other as shown in FIG. 15B. Further, the output terminals OUT1 to OUT4 of the inductor elements L1 to L4 are also connected to each other as shown in FIG. Therefore, the inductor elements L1 to L4 are connected in parallel.

  The inductor element L1 includes inductor element pieces L11 to L13 that are sequentially connected in series from the input terminal IN1 to the output terminal OUT1. Similarly, the inductor element L2 includes inductor element pieces L21 to L23 that are sequentially connected in series from the input terminal IN2 to the output terminal OUT2. The inductor element L3 is also configured by inductor element pieces L31 to L33 that are sequentially connected in series from the input terminal IN3 to the output terminal OUT3. The inductor element L4 is also configured by inductor element pieces L41 to L43 that are sequentially connected in series from the input terminal IN4 to the output terminal OUT4. Each inductor element piece makes one turn in each layer, and adjacent inductor element pieces connected in series are connected via vias A1 to A4 and B1 to B4.

  Although the present embodiment has been described for the case of four inductor elements, the present invention is effective for any even number of inductor elements. Note that, regardless of the total number of even number of inductor elements, the input terminals of half of the inductor elements are in the uppermost layer and the output terminals are in the lowermost layer, and the input terminals of the other half of the inductor elements are in the lowermost layer. In addition, the output terminal is on the uppermost layer, the input terminals are connected to each other, and the output terminals are connected to each other.

  The inductor according to the fourth embodiment of the present invention is characterized in that the inductor element piece in a certain layer is wider than the inductor element piece in the upper layer.

  Referring to FIG. 16, the on-chip type inductor according to the fifth embodiment of the present invention has two inductor elements L1 and L2. The inductor element L1 extends spirally from an input terminal (not shown) to an output terminal over two layers through the insulating layer IS. The inductor element L2 also extends spirally from an input terminal (not shown) to the output terminal over two layers through the insulating layer IS. The inductor elements L1 and L2 are arranged so that the generated magnetic fields are in the same direction, and the inductor characteristics including the Q value viewed from the input terminal are substantially the same as those viewed from the output terminal. Connected in parallel.

  More specifically, the inductor element L1 and the inductor element L2 are not shown in FIG. 16, but have substantially the same shape in plan view, and are mutually in the rotational direction with respect to a common center point (not shown). It is arranged almost without deviation. The inductor element L1 has an input terminal on the uppermost layer of the two layers and an output terminal on the lowermost layer. On the other hand, the inductor element L2 has an input terminal at the lowermost layer of the plurality of layers and an output terminal at the uppermost layer. Further, although not shown, the input terminal of the inductor element L1 and the input terminal of the inductor element L2 are connected to each other. The output terminal of the inductor element L1 and the output terminal of the inductor element L2 are also connected to each other. Therefore, the inductor elements L1 and L2 are connected in parallel. The inductor element L2 includes inductor element pieces L21 and L22 that are sequentially connected in series from the input terminal to the output terminal. Similarly, the inductor element L1 includes inductor element pieces L11 and L12 that are sequentially connected in series from the input terminal to the output terminal. Each inductor element piece makes one turn in each layer, and adjacent inductor element pieces connected in series are connected to each other via vias (not shown).

  In particular, in the present inductor, the inductor element piece in the lower layer as the second layer below the upper layer as the first layer is wider than the inductor element piece in the upper layer. That is, the inductor element piece L12 of the inductor element L1 is wider than the inductor element piece L11 in the upper layer. Similarly, the inductor element piece L21 of the inductor element L2 is wider than the inductor element piece L22 in the upper layer.

  The present embodiment is an approach different from that of the second embodiment for the same purpose as the second embodiment. That is, in the present embodiment, the width of the wiring formed in the lower layer of the inductor is made as wide as possible as compared with the wiring formed in the upper layer, so that even a lower layer wiring having a small thickness is substantially larger. A cross-sectional area is obtained, and thus a low wiring resistance is realized.

  The inductor according to the fifth embodiment of the present invention is characterized in that the inductor element piece in a certain circumference is wider than the inductor element piece in the inner circumference.

  Referring to FIG. 17, the on-chip type inductor according to the fifth embodiment of the present invention has two inductor elements L1 and L2. The inductor element L1 spirally extends from the input terminal IN1 to the output terminal OUT1 over two layers with an insulating layer interposed therebetween. The inductor element L2 also extends spirally from the input terminal IN2 to the output terminal OUT2 over two layers with an insulating layer interposed therebetween. The inductor elements L1 and L2 are arranged so that the generated magnetic fields are in the same direction, and the inductor characteristics including the Q value viewed from the input terminal are substantially the same as those viewed from the output terminal. Connected in parallel.

  More specifically, the inductor element L1 and the inductor element L2 have substantially the same shape in plan view, and are disposed substantially without mutual displacement in the rotation direction with respect to the common center point X. The inductor element L1 has an input terminal IN1 in the uppermost layer of the three layers and an output terminal OUT1 in the lowermost layer. On the other hand, the inductor element L2 has an input terminal IN2 in the lowermost layer of the plurality of layers and an output terminal OUT2 in the uppermost layer. Although not shown in FIG. 17, the input terminal IN1 of the inductor element L1 and the input terminal IN2 of the inductor element L2 are connected to each other. The output terminal OUT1 of the inductor element L1 and the output terminal OUT2 of the inductor element L2 are also connected to each other. Therefore, the inductor elements L1 and L2 are connected in parallel. The inductor element L1 includes inductor element pieces L11 and L12 that are sequentially connected in series from the input terminal IN1 to the output terminal OUT1. Inductor element pieces L11 and L12 each circulate once in two layers, and adjacent inductor element pieces connected in series are connected to each other via via A1. The inductor element L2 includes inductor element pieces L21 and L22 that are sequentially connected in series from the input terminal IN2 to the output terminal OUT2. Inductor element pieces L21 and L22 each make one turn in the two layers, and adjacent inductor element pieces connected in series are connected to each other via via A2.

  In particular, in this inductor, the inductor element on the outer periphery of the inductor elements is wider than the inductor element on the inner periphery at least in part. That is, although not shown in FIG. 17, the inductor element L1 on the outer periphery of the inductor elements L1 and L2 is wider than the inductor element L2 on the inner periphery in at least a part of its length range.

  This is to eliminate the fact that the path length of the inductor element on the outer periphery is longer than that of the inductor element on the inner periphery and the series resistance is increased. Therefore, the length range to be wide and the width dimension to be increased should be set so that the series resistances of the inner and outer inductor elements are equal to each other.

  The sixth embodiment of the present invention is an example in which a VCO (Voltage Controlled Oscillator) is configured using the present inductor as an application example of the inductor according to the present invention.

  FIG. 18 is a circuit diagram of a VCO (Voltage Controlled Oscillator). The VCO is a circuit that changes the oscillation frequency by changing the voltage applied to the point VCNT in the figure. In the figure, MN1 and MN2 are nMOSFETs, MP1 and MP2 are pMOSFETs, VC1 and VC2 are variable capacitors, IS1 is a constant current source, and L is an inductor. As is clear from FIG. 18, symmetry is important for this circuit because it performs differential operation.

  In the oscillation circuit according to the present invention, a fixed capacitor may be used instead of the variable capacitors VC1 and VC2. In the oscillation circuit according to the present invention, the capacitors such as the variable capacitors VC1 and VC2 may be an on-chip type provided in a chip-type semiconductor device like the inductor according to the present invention, or may be a chip type. The semiconductor device may be a separate device. Furthermore, in the oscillation circuit according to the present invention, the capacitor is not limited to being connected in parallel to the inductor as shown in FIG. 18, but may be connected in series.

  As an inductor L connected between the terminals LO1 and LO2, parameters of an on-chip type inductor to a 90 nm generation MOSFET, in particular, an inductor according to the present invention and a multilayer series connection type inductor as a comparative example are applied. A VCO simulation was performed. An electronic circuit simulator SPICE (Simulation Program with Integrated Circuit Emphasis) was used for the calculation.

  FIG. 19 shows, as a simulation result, changes with time of voltages at the terminals LO1 and LO2 when the parameters of the inductor according to the present invention are applied. FIG. 20 shows the change over time in the voltages at the terminals LO1 and LO2 when the parameters of the inductor of the multilayer series connection method are applied as simulation results.

  As apparent from FIGS. 19 and 20, the multi-layer series connection type inductor is inferior in symmetry, so that the difference in the average value of the potential between the terminal LO1 and the terminal LO2 becomes large, and the oscillation amplitude of the VCO attenuates with time. Then oscillation stops. On the other hand, since the inductor according to the present invention is excellent in symmetry, the difference in the average value of the potential is small and the oscillation continues.

  Thus, the present invention is also suitable for applications that require symmetry such as differential circuits.

  The present invention is not limited to the embodiments described above, and it goes without saying that various modifications are possible within the technical scope described in the claims.

(A) is a top view of the inductor of the planar structure of related technology, (b) is sectional drawing of this inductor along the cutting line 1B-1B in Fig.1 (a). It is sectional drawing of the inductor of a related art multilayer series connection system. It is a conceptual top view of the inductor of the related art multilayer series connection system. (A) is a top view of the inductor of the planar structure of related technology, (b) is sectional drawing of this inductor along the cutting line 4B-4B in Fig.4 (a). (A) is a conceptual top view of the inductor by Example 1 of this invention, (b) is an equivalent figure of this inductor. It is sectional drawing of the inductor by Example 2 of this invention. (A) is the perspective view which showed transparently the inner layer of the inductor by this invention, (b) is a notional top view of this inductor, (c) is sectional drawing of this inductor. is there. (A) is the perspective view which showed transparently the inner layer of the inductor of the multilayer serial connection system as a comparative example, (b) is a notional top view of this inductor, (c), It is sectional drawing of this inductor. (A) is the perspective view which showed transparently the inner layer of the inductor of the multilayer serial connection system as a comparative example, (b) is a notional top view of this inductor, (c), It is sectional drawing of this inductor. It is an LCR equivalent diagram of an inductor. It is a figure which shows the series inductance of the inductor of this invention, and the inductor of two comparative examples. It is a figure which shows the Q value of the inductor of this invention, and the inductor of two comparative examples. It is a figure which shows the parasitic capacitance of the inductor of this invention, and the inductor of two comparative examples. It is a figure which shows the series resistance of the inductor of this invention, and the inductor of two comparative examples. (A) is a conceptual top view of the inductor by Example 3 of this invention, (b) is an equivalent figure of this inductor. It is sectional drawing of the inductor by Example 4 of this invention. It is a notional top view of the inductor by Example 5 of the present invention. It is a circuit diagram which shows the voltage controlled oscillation circuit using this inductor as Example 6 of this invention. It is a figure which shows the result of the simulation in the circuit shown by FIG. 18 about the inductor by this invention. It is a figure which shows the result of the simulation in the circuit shown by FIG. 18 about the inductor of a multilayer serial connection system.

Explanation of symbols

A, A1-A4, B, B1-B4 Via C1, C2 Wiring capacitance IN, IN1-IN4 Input terminal IS Insulating layer IS1 Current source L0 Inductance L1-L4, L, L ', L ", LL Inductor element MN1, MN2 nMOSFET
MP1, MP2 pMOSFET
OUT, OUT1-OUT4 Output terminal R0 Wiring resistance SL Slit VC1, VC2 Variable capacitance

Claims (10)

An on-chip inductor used in a chip-type semiconductor device,
Having an even number of inductor elements each extending spirally from the input terminal to the output terminal across a plurality of layers via an insulating layer;
The even number of inductor elements are arranged so that the generated magnetic fields are in the same direction, and the inductor characteristics including the Q value viewed from the input terminal are substantially the same as those viewed from the output terminal. The inductor is characterized by being connected in parallel. The even number of inductor elements are substantially congruent with each other in a plan view, and are arranged substantially without mutual displacement in the rotation direction with respect to a common center point,
Half of the even number of inductor elements, the input terminal is in the uppermost layer of the plurality of layers, the output terminal is in the lowermost layer,
The other half of the even number of inductor elements has the input terminal at the bottom layer of the plurality of layers and the output terminal at the top layer,
The inductor according to claim 1, wherein the input terminals of the even number of inductor elements are connected to each other and the output terminals are connected to each other. Each of the even number of inductor elements is constituted by a plurality of inductor element pieces sequentially connected in series from the input terminal to the output terminal,
3. The plurality of inductor element pieces each circulate once in the plurality of layers, and adjacent inductor element pieces connected in series are connected to each other via vias. Inductor. The inductor element pieces in the second layer, which is lower than the first layer of the plurality of layers, have a congruent shape in plan view and are arranged without deviation in the rotation direction with respect to a common center point An additional inductor element piece in a third layer that is lower than the second layer,
The inductor according to claim 3, wherein the additional inductor element piece is connected in parallel to the inductor element piece in the second layer via a via.   4. The inductor according to claim 3, wherein an inductor element piece in a second layer that is lower than a first layer of the plurality of layers is wider than an inductor element piece in the first layer.   The inductor according to any one of claims 1 to 5, wherein an inductor element on an outer periphery of the even number of inductor elements is wider than an inductor element on an inner periphery at least in part.   A plurality of wiring layers stacked via an insulating layer and the inductor according to any one of claims 1 to 6, wherein the inductor element is any two or more of the plurality of wiring layers. A wiring board comprising:   A chip comprising: a wiring board; an active component mounted on the wiring board; and the inductor according to any one of claims 1 to 6 as a passive component mounted on the wiring board. Type semiconductor device.   7. An oscillation circuit comprising: the inductor according to claim 1; and a capacitor having a fixed or variable capacitance value connected in parallel or in series to the inductor. An on-chip inductor used in a chip-type semiconductor device,
Having an even number of inductor elements each extending spirally from the input terminal to the output terminal across a plurality of layers via an insulating layer;
The even number of inductor elements are substantially congruent with each other in a plan view, and are arranged substantially without mutual displacement in the rotation direction with respect to a common center point,
Half of the even number of inductor elements, the input terminal is in the uppermost layer of the plurality of layers, the output terminal is in the lowermost layer,
The other half of the even number of inductor elements has the input terminal at the bottom layer of the plurality of layers and the output terminal at the top layer,
The inductor, wherein the input terminals of the even number of inductor elements are connected to each other and the output terminals are connected to each other.

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