KR102421174B1 - An low-power high-speed ILFM for advanced clocking applications - Google Patents

Abstract

A low-power, high-speed ILFM for advanced clocking applications is presented. The low-power, high-speed ILFM for an improved clocking application proposed by the present invention includes an input transistor (M3, M4) that receives an input signal, a plurality of inductors (L1, L2, L3, and L4) for generating a high-frequency clock, and the generated high-frequency clock output transistors M1 and M2 for outputting , and a plurality of inductors are laid out as a single distributed inductor by combining an on-chip inductor to generate a high-frequency clock.

Description

An low-power high-speed ILFM for advanced clocking applications

The present invention relates to a low power high speed ILFM for advanced clocking applications.

Injection-Locked Frequency Multipliers (ILFMs) are useful analog circuit blocks for Phase-Locked Loops (PLLs) because of their low power consumption and great advantages for high-speed signal generation compared to current-mode logic multipliers. Therefore, ILFM may be suitable for high-speed communication interfaces of memory or mobile devices. However, the ILFM of the prior art having a complex structure includes a large number of inductors, consumes a huge amount of power, and expands the chip area.

Prior art ILFM uses many passive inductors and transformers to generate high frequency clocks for high speed data communication interfaces. The architecture of the previous ILFM uses many passive inductors with large chip size and parasitic capacitance resulting from complex routing between inductors.

The technical problem to be achieved by the present invention is to provide a low-power, high-speed ILFM for generating a high-frequency clock for a high-speed data communication interface while reducing the chip area and power consumption due to a plurality of inductors in the ILFM of the prior art having a complex structure. have.

In one aspect, the low-power, high-speed ILFM for an improved clocking application proposed by the present invention is an input transistor (M3, M4) that receives an input signal, and a plurality of inductors (L1, L2, L3 and L4) for generating a high-frequency clock. and output transistors M1 and M2 for outputting the generated high frequency clock, wherein the plurality of inductors are laid out as a single distributed inductor by combining an on-chip inductor to generate a high frequency clock.

As for the plurality of inductors, the first inductor L1 and the second inductor L2 are laid out on the first metal layer, and the third inductor L3 and the fourth inductor L4 are laid out on the second metal layer.

Multiple inductors are laid out as a single distributed inductor to reduce chip area and eliminate long metal routing wires between adjacent inductors.

Multiple inductors are laid out as a single distributed inductor by combining on-chip inductors for high-frequency clock generation, increasing the efficiency of signal coupling, preventing signal degradation, and providing a symmetrical impedance to the active circuit.

The low-power high-speed ILFM according to an embodiment of the present invention reduces power consumption by operating in a near-threshold voltage (NTV) operating region.

A high-frequency clock is generated by scaling the size of a plurality of inductors that are laid out as a single distributed inductor.

According to embodiments of the present invention, it is possible to improve chip area efficiency and eliminate long metal routing wires between adjacent inductors by combining an on-chip inductor to utilize a single distributed inductor. It can also improve the efficiency of signal coupling, prevent signal degradation, and provide a perfectly symmetrical impedance to the active circuit.

1 is a diagram illustrating a circuit of a low-power, high-speed ILFM for an improved clocking application according to an embodiment of the present invention.
2 is a waveform showing input and output clock signals in the frequency domain and the time domain of the ILFM according to an embodiment of the present invention.
3 is a diagram illustrating a layout of a low-power, high-speed ILFM for an improved clocking application according to an embodiment of the present invention.

Injection-Locked Frequency Multipliers (ILFMs) are useful analog circuit blocks for Phase-Locked Loops (PLLs) because of their low power consumption and great advantages for high-speed signal generation compared to current-mode logic multipliers. Therefore, ILFM may be suitable for high-speed communication interfaces of memory or mobile devices. However, the ILFM of the prior art having a complex structure includes a large number of inductors, consumes a huge amount of power, and expands the chip area.

According to an embodiment of the present invention, a novel ILFM architecture with a single distributed inductor is proposed to provide a high frequency clock with low power consumption and smaller chip size. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a circuit of a low-power, high-speed ILFM for an improved clocking application according to an embodiment of the present invention.

Figure 1 (a) is a circuit of a low-power high-speed ILFM for an improved clocking application according to an embodiment of the present invention, Figure 1 (b) is a single distributed inductor (Single Distributed Inductor) according to an embodiment of the present invention It is a diagram showing the layout and circuit of

Low-power, high-speed, injection-locked frequency multipliers (ILFMs) for advanced clocking applications include an input transistor (M3, M4) that receives an input signal, a plurality of inductors (L1, L2, L3, and L4) for generating a high-frequency clock, and a and output transistors M1 and M2 for outputting a high-frequency clock.

The plurality of inductors L1, L2, L3, and L4 are laid out as a single distributed inductor by combining on-chip inductors to generate a high-frequency clock.

According to an embodiment of the present invention, the first inductor L1 and the second inductor L2 among the plurality of inductors L1, L2, L3 and L4 are laid out on the first metal layer Metal8, and the third inductor ( L3) and the fourth inductor L4 may be laid out on the second metal layer Metal7.

Multiple inductors L1, L2, L3 and L4 are laid out as a single distributed inductor to reduce chip area and eliminate long metal routing wires between adjacent inductors.

A plurality of inductors (L1, L2, L3, and L4) are laid out as a single distributed inductor by combining the on-chip inductors for high-frequency clock generation, increasing the efficiency of signal coupling, preventing signal degradation, and providing a symmetrical impedance to the active circuit. to provide.

The low-power, high-speed ILFM according to an embodiment of the present invention can reduce power consumption by operating in a near-threshold voltage (NTV) operating region. A high-frequency clock can be generated by scaling the sizes of a plurality of inductors that are laid out as a single distributed inductor.

Since the power P can be expressed as P=CV ^2f , by operating in the NTV (Near-Threshold Voltage) operating region, it is possible to reduce power consumption by about 3 to 5 times compared to the conventional technology.

For high-frequency clock generation, it is necessary to utilize many inductors. However, the proposed ILFM utilizes a single distributed inductor by combining an on-chip inductor as shown in Fig. 1(b). The advantages of the proposed ILFM topology are that it can improve chip area efficiency and eliminate long metal routing wires between adjacent inductors. Therefore, the proposed ILFM improves the efficiency of signal coupling, prevents signal degradation, and provides a perfectly symmetrical impedance to the active circuit. In addition, the proposed ILFM operates in a near-threshold voltage (NTV) operating region where the power supply operates at a low supply voltage (eg, 0.5V to 0.6V). Because the power is proportional to the square of the supply voltage, the power consumption of the ILFM can be greatly reduced. In addition, by scaling the size of the distributed inductor, the proposed ILFM injects a low-frequency input signal (eg, 0.8 GHz to 3.6 GHz) for a future high-speed communication system, thereby providing a very high-frequency output clock signal (eg, , from 5 GHz to 36 GHz).

2 is a waveform showing input and output clock signals in the frequency domain and time domain of the ILFM according to an embodiment of the present invention.

Fig. 2(a) shows the simulated input clock signal 211 and the output clock signal 212 in the frequency domain of the proposed ILFM, and Fig. 2(b) is the simulated input clock signal in the time domain of the proposed ILFM. A signal 221 and an output clock signal 222 are shown. The highest frequency clock signal (eg up to 36 GHz) can be generated at a 1 GHz clock.

3 is a diagram illustrating a layout of a low-power, high-speed ILFM for an improved clocking application according to an embodiment of the present invention.

Referring to FIG. 3 , a layout of an ILFM according to an embodiment of the present invention is shown in 28 nm CMOS technology. The layout area of the proposed distributed inductor is generally dominant in the entire chip area. Therefore, by using a single distributed inductor, the proposed ILFM provides a much smaller layout area than the conventional ILFM.

<Table 1>

Table 1 shows the performance comparison between the ILFM proposed in the prior art and the existing ILFM. ILFM can deliver much higher frequency clocks within 60% of power consumption.

The proposed ILFM architecture can provide a high-frequency and low-power clock system for high data rate communication in future applications.

For high-sensitivity and high-quality circuit construction, an inductor or transformer signal coupler with a high Q-factor is required. A larger number of inductors are required for frequency multiplication and frequency division, and in the conventional technology, signal degradation is exacerbated due to parasitic resistance components generated in the connection between each inductor and the transformer.

In frequency multiplication and frequency division, high-performance frequency multiplication and frequency division are possible with a multi-stage amplification stage using multiple stages of MOS transistors, but this also increases power consumption, and the chip area is exponentially increased. The increase has its drawbacks.

Therefore, in injection-locked frequency multipliers (ILFM) and frequency division proposed in the present invention, a multi-layer single distributed inductor is used to improve these problems, and sub-harmonics are used to reduce the amplification stages of multiple stages. By merging sub-harmonic frequecy division and frequency multiplication technology, the chip area can be dramatically reduced and signal degradation caused by parasitic resistances or capacitors can also be reduced.

The device described above may be implemented as a hardware component, a software component, and/or a combination of the hardware component and the software component. For example, devices and components described in the embodiments may include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), It may be implemented using one or more general purpose or special purpose computers, such as a programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For convenience of understanding, although one processing device is sometimes described as being used, one of ordinary skill in the art will recognize that the processing device includes a plurality of processing elements and/or a plurality of types of processing elements. It can be seen that may include For example, the processing device may include a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as parallel processors.

Software may comprise a computer program, code, instructions, or a combination of one or more of these, which configures a processing device to operate as desired or is independently or collectively processed You can command the device. The software and/or data may be any kind of machine, component, physical device, virtual equipment, computer storage medium or device, to be interpreted by or to provide instructions or data to the processing device. may be embodied in The software may be distributed over networked computer systems and stored or executed in a distributed manner. Software and data may be stored in one or more computer-readable recording media.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the medium may be specially designed and configured for the embodiment, or may be known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic such as floppy disks. - includes magneto-optical media, and hardware devices specially configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter or the like.

As described above, although the embodiments have been described with reference to the limited embodiments and drawings, various modifications and variations are possible by those skilled in the art from the above description. For example, the described techniques are performed in a different order than the described method, and/or the described components of the system, structure, apparatus, circuit, etc. are combined or combined in a different form than the described method, or other components Or substituted or substituted by equivalents may achieve an appropriate result.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (6)

input transistors M3 and M4 for receiving an input signal;
a plurality of inductors L1, L2, L3 and L4 for generating a high-frequency clock; and
Output transistors (M1, M2) for outputting the generated high-frequency clock
including,
A plurality of inductors,
It is laid out as a single distributed inductor by combining an on-chip inductor for high-frequency clock generation.
The first inductor L1 and the second inductor L2 are laid out on the first metal layer,
The third inductor L3 and the fourth inductor L4 are laid out on the second metal layer,
One end of the first inductor (L1) is connected to the first output transistor (M1), the other end of the first inductor (L1) is connected to the third inductor (L3),
One end of the second inductor L2 is connected to the second output transistor M2, and the other end of the second inductor L2 is connected to the fourth inductor L4,
Another end of the third inductor (L3) and the fourth inductor (L4) are connected to each other
Low-power, high-speed injection-locked frequency multipliers (ILFMs). delete According to claim 1,
A plurality of inductors,
It is laid out as a single distributed inductor to reduce chip area and eliminate long metal routing wires between adjacent inductors.
Low-power, high-speed ILFM. According to claim 1,
Multiple inductors are laid out as a single distributed inductor by combining on-chip inductors for high-frequency clock generation, which increases the efficiency of signal coupling, prevents signal degradation, and provides a symmetrical impedance to the active circuit.
Low-power, high-speed ILFM. According to claim 1,
Low-power high-speed ILFM,
By operating in NTV (Near-Threshold Voltage) operating area, it reduces power consumption.
Low-power, high-speed ILFM. According to claim 1,
A high-frequency clock is generated by scaling the size of a plurality of inductors laid out as a single distributed inductor.
Low-power, high-speed ILFM.

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