JPS60221757A - Mask for exposure - Google Patents
Mask for exposureInfo
- Publication number
- JPS60221757A JPS60221757A JP60030354A JP3035485A JPS60221757A JP S60221757 A JPS60221757 A JP S60221757A JP 60030354 A JP60030354 A JP 60030354A JP 3035485 A JP3035485 A JP 3035485A JP S60221757 A JPS60221757 A JP S60221757A
- Authority
- JP
- Japan
- Prior art keywords
- mask
- reticle
- patterns
- kinds
- effective area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は露光用マスク、特に縮小投影露光用マスクすな
わちレチクルなどに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an exposure mask, and particularly to a reduction projection exposure mask, such as a reticle.
半導体装置の製造において、半導体基板表面の選択的な
拡散、酸化、エツチングのために基板表面に塗布された
。有機感光剤への光学処理のためにマスクアライナが使
用される。In the manufacture of semiconductor devices, it is applied to the surface of a semiconductor substrate for selective diffusion, oxidation, and etching. A mask aligner is used for optical processing of organic photosensitizers.
従来のマスクアライナを投影方式により大別すると、(
1)マスクのパターンをウェハ面に1:】の比で投影さ
せる方式及び(2)マスクのパターンを例えば1/10
に縮小してウエノ・面に移動投影する方式とがある。こ
のうち(1)は一つのマスタマスクに例えば200チッ
プ分のパターンを配列したものを使用するもので投光時
間は約10秒と短いが被処理物と同寸法の微細なパター
ンであるため解像度に限界があり、精密なパターンのマ
スクの製作が困難である。これに対して(2)は第1図
に示すように一つのマスク1に一つのチップに対する約
10倍の寸法を有するパターン2を配列したものを使用
するので極めて高い精度のものが得られ、投光用光量も
少なくてすむが、第2図に示すように一つのウェハ3に
対してマスクをXY方向に相対移動させながら例えば2
00チップ分の投影を順次行なうため処理時間が長く、
例えば20分を ′要する。このような縮小投影アライ
ナは少量生産品種、特急試作品種のごとく大量につくる
よりも速急につくることを要求される場合に特に問題と
なる。Conventional mask aligners can be broadly categorized by projection method: (
1) A method in which the mask pattern is projected onto the wafer surface at a ratio of 1: ], and (2) a method in which the mask pattern is projected onto the wafer surface at a ratio of, for example, 1/10.
There is a method in which the image is reduced in size and moved and projected onto a surface. Of these, (1) uses one master mask with patterns for, say, 200 chips arranged, and the light emission time is short, about 10 seconds, but the pattern is fine and has the same dimensions as the object to be processed, so the resolution is high. There are limits to this, making it difficult to produce masks with precise patterns. On the other hand, (2) uses a mask 1 in which a pattern 2 having a size approximately 10 times that of one chip is arranged as shown in FIG. 1, so extremely high precision can be obtained. The amount of light for projection can also be small, but as shown in FIG.
The processing time is long because the projections for 00 chips are performed sequentially.
For example, it takes 20 minutes. Such reduction projection aligners are particularly problematic when they are required to be produced more quickly than in large quantities, such as in small-volume production types or express prototype types.
たとえば、パターンが1%け書かれているレチクルにつ
いては、電子材料1983年3月号、p。For example, regarding a reticle with a pattern written in 1% digits, see Denshi Materials March 1983 issue, p.
−72〜78に記載されている。-72 to 78.
本発明は上記した従来技術の問題点を解決するべくなさ
れたものであり、本発明の目的は縮小投影露光装置に使
用し作業時間を全体的に短縮できるマスク、すなわちレ
チクルを提供することなどにある。The present invention has been made in order to solve the problems of the prior art described above, and an object of the present invention is to provide a mask, that is, a reticle, which can be used in a reduction projection exposure apparatus and can shorten the overall working time. be.
上記目的を達成するため本発明の一実施例は一枚のレチ
クル内の有効領域に複数個の品種の異なるバターを配置
することにより同じ工程で2品種以上を同時に処理し、
工程全体を短縮化することなどを要旨とする。In order to achieve the above object, one embodiment of the present invention processes two or more types of butter simultaneously in the same process by arranging a plurality of different types of butter in an effective area within one reticle,
The main idea is to shorten the entire process.
第3図に本発明の一実施例による縮小投影アライナ用マ
スクの構造の一例を示す。同図において、4はレチクル
、5の一点鎖線内はレチクル内の有効領域すなわち縮小
レンズの有効径を示す。この有効領域内に複数個の品種
の異なるパターンA。FIG. 3 shows an example of the structure of a mask for a reduction projection aligner according to an embodiment of the present invention. In the figure, reference numeral 4 indicates a reticle, and the area within the dashed line 5 indicates an effective area within the reticle, that is, an effective diameter of the reduction lens. Within this effective area, there are a plurality of different patterns A of different types.
B、Cが設けられる。このA、B、Cは処理される半導
体ウェハ表面の同じ層に属し、同じ工程で処理されるも
のである。B and C are provided. These A, B, and C belong to the same layer on the surface of the semiconductor wafer to be processed, and are processed in the same process.
このようなレチクルを使用することにより、第5図(a
)に示すように3品種のパターンを同時にウェハ内に焼
き込むことができ、従来、一つのレチクルで1つのパタ
ーンしかないために3品種のパターンの焼付けにはその
3倍の手間と時間が必要であったが、本発明の一実施例
では1回ですみ、工程数が大幅に短縮できる。同図(b
) 、 (c)は1つのレチクルにおける品種の異なる
パターンを2種又は1種のみ取出して選択的に焼付ける
場合で、選択用マスク(遮蔽板)を使用する。By using such a reticle, the image shown in FIG.
), three types of patterns can be printed on the wafer at the same time, and since there was only one pattern per reticle, printing three types of patterns required three times as much effort and time as conventional methods. However, in one embodiment of the present invention, only one step is required, and the number of steps can be significantly reduced. The same figure (b
) and (c) are cases in which two or only one type of patterns of different types from one reticle are taken out and selectively printed, and a selection mask (shielding plate) is used.
第4図は本発明の一実施例に使用される縮小投影アライ
ナにおけるマスク支持枠6を示し、支持枠中にマスク(
レチクル)4を固定し、遮蔽板7を開閉することによっ
てマスクの異なるパターンごとの選択的投影を可能とし
たものである。FIG. 4 shows a mask support frame 6 in a reduction projection aligner used in one embodiment of the present invention, and the mask (
By fixing the reticle 4 and opening and closing the shielding plate 7, it is possible to selectively project different patterns on the mask.
このような本発明の一実施例によれば、縮小投光方式の
長所である精度の良さを有するとともに、異なる品種の
パターンを同時に焼付けることにより少量の多種生産の
場合の工程数を短縮することが可能となった。又、本発
明の一実施例によ4ば縮小投光アライナとして、複数個
の品種の異なるパターンを有するレチクルを使用し、異
なるパターン毎の選択的投影を可能ならしめ、その際マ
スクセツティング時間を節約することができ特に少量の
試作品を特急に処理する場合などに有効である。According to such an embodiment of the present invention, it has the high precision that is an advantage of the reduction projection method, and also shortens the number of processes in the case of small-lot, multi-product production by printing patterns of different types at the same time. It became possible. Furthermore, according to an embodiment of the present invention, reticles having different patterns of a plurality of types are used as a reduction projection aligner to enable selective projection of each different pattern, and in this case, the mask setting time is reduced. This is especially effective when processing small quantities of prototypes on an express basis.
第1図は従来の縮小投影アライナ用レチクルの形態を示
す平面図、第2図は縮小投影アライナの原理的構造を示
す概略図、第3図は本発明の一実施例による縮小投影ア
ライナ用マスクの形態を示す平面図、第4図は本発明の
一実施例に使用する縮小投影アライナのマスク支持部を
示す概略断面図、第5図(a) 、 (b) 、 (c
)は本発明の一実施例による縮小投影マスクの異種パタ
ーンを選択的に取出す場合の形態を示す平面図である。
1・・・マスク、2・・・パターン、3・・・ウェハ、
4・・・レチクル、訃・・有効領域、6・・・マスク支
持枠、7・・・開閉する遮蔽板、A、B、C・・・品種
ごとに異なるパターン。
□×Y
第 312J
第 5 崗
(a−> (b) (c)FIG. 1 is a plan view showing the form of a conventional reticle for a reduction projection aligner, FIG. 2 is a schematic diagram showing the principle structure of a reduction projection aligner, and FIG. 3 is a mask for a reduction projection aligner according to an embodiment of the present invention. FIG. 4 is a schematic sectional view showing a mask support part of a reduction projection aligner used in one embodiment of the present invention, and FIGS. 5(a), (b), (c)
) is a plan view showing a form in which different types of patterns are selectively extracted from a reduction projection mask according to an embodiment of the present invention. 1...Mask, 2...Pattern, 3...Wafer,
4... Reticle, butt... effective area, 6... mask support frame, 7... shielding plate that opens and closes, A, B, C... different patterns for each product. □×Y No. 312J No. 5 (a-> (b) (c)
Claims (1)
露光用レチクル。 2、上記複数個のパターンは少なくとも2つの異なるパ
ターンを有することを特徴とする特許請求の範囲第1項
記載の縮小投影露光用レチクル。[Claims] 1. A reticle for reduction projection exposure characterized by having a plurality of patterns. 2. The reticle for reduction projection exposure according to claim 1, wherein the plurality of patterns have at least two different patterns.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60030354A JPS60221757A (en) | 1985-02-20 | 1985-02-20 | Mask for exposure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60030354A JPS60221757A (en) | 1985-02-20 | 1985-02-20 | Mask for exposure |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3548779A Division JPS55129333A (en) | 1979-03-28 | 1979-03-28 | Scale-down projection aligner and mask used for this |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62226314A Division JPS6379318A (en) | 1987-09-11 | 1987-09-11 | Reduction projection exposure method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60221757A true JPS60221757A (en) | 1985-11-06 |
JPS6155106B2 JPS6155106B2 (en) | 1986-11-26 |
Family
ID=12301513
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60030354A Granted JPS60221757A (en) | 1985-02-20 | 1985-02-20 | Mask for exposure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60221757A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6362229A (en) * | 1986-09-03 | 1988-03-18 | Canon Inc | Aligner |
WO1999009456A1 (en) * | 1997-08-19 | 1999-02-25 | Micron Technology, Inc. | Multiple image reticle for forming layers |
US6368754B1 (en) | 1998-11-13 | 2002-04-09 | Nec Corporation | Reticle used for fabrication of semiconductor device |
CN102902155A (en) * | 2011-07-29 | 2013-01-30 | 株式会社V技术 | Photomask and exposure device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3704946A (en) * | 1969-02-20 | 1972-12-05 | Opt Omechanisms Inc | Microcircuit art generating means |
-
1985
- 1985-02-20 JP JP60030354A patent/JPS60221757A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3704946A (en) * | 1969-02-20 | 1972-12-05 | Opt Omechanisms Inc | Microcircuit art generating means |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6362229A (en) * | 1986-09-03 | 1988-03-18 | Canon Inc | Aligner |
WO1999009456A1 (en) * | 1997-08-19 | 1999-02-25 | Micron Technology, Inc. | Multiple image reticle for forming layers |
US5995200A (en) * | 1997-08-19 | 1999-11-30 | Micron Technology, Inc. | Multiple image reticle for forming layers |
US6040892A (en) * | 1997-08-19 | 2000-03-21 | Micron Technology, Inc. | Multiple image reticle for forming layers |
US6421111B1 (en) | 1997-08-19 | 2002-07-16 | Micron Technology, Inc. | Multiple image reticle for forming layers |
US6563568B2 (en) | 1997-08-19 | 2003-05-13 | Micron Technology, Inc. | Multiple image reticle for forming layers |
US6646722B2 (en) | 1997-08-19 | 2003-11-11 | Micron Technology, Inc. | Multiple image reticle for forming layers |
US6368754B1 (en) | 1998-11-13 | 2002-04-09 | Nec Corporation | Reticle used for fabrication of semiconductor device |
CN102902155A (en) * | 2011-07-29 | 2013-01-30 | 株式会社V技术 | Photomask and exposure device |
JP2013029749A (en) * | 2011-07-29 | 2013-02-07 | V Technology Co Ltd | Photo mask and exposure device |
Also Published As
Publication number | Publication date |
---|---|
JPS6155106B2 (en) | 1986-11-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS55129333A (en) | Scale-down projection aligner and mask used for this | |
US4397543A (en) | Mask for imaging a pattern of a photoresist layer, method of making said mask, and use thereof in a photolithographic process | |
JPH09134870A (en) | Method and device for forming pattern | |
JPS60221757A (en) | Mask for exposure | |
US20030039928A1 (en) | Multiple purpose reticle layout for selective printing of test circuits | |
JPH05243115A (en) | Manufacture of semiconductor device | |
JPH01234850A (en) | Photomask for semiconductor integrated circuit | |
JPH01293616A (en) | Manufacture of semiconductor integrated circuit | |
JPH0620903A (en) | Manufacture of semiconductor device | |
JPS60221758A (en) | Exposing method by reducing projection | |
JPH03237459A (en) | Exposing method for semiconductor wafer and reticule for step exposing | |
JP2002373845A (en) | Electron beam exposure method and apparatus thereof | |
JPH01134919A (en) | Optical stepper | |
JP2715462B2 (en) | Reticle and method of manufacturing semiconductor device using the same | |
JPS6379318A (en) | Reduction projection exposure method | |
JPS63278230A (en) | Manufacture of semiconductor device | |
JPH0545944B2 (en) | ||
JP2545431B2 (en) | Lithography reticle and reticle pattern transfer method | |
JPH04304453A (en) | Reticle and exposing method | |
JP2005017314A (en) | Exposure mask and method for manufacturing semiconductor device | |
JPS6341050B2 (en) | ||
JPH022556A (en) | Stepper reticle for semiconductor device manufacture | |
JPS6179227A (en) | Pattern forming method using photo resist | |
US6410350B1 (en) | Detecting die speed variations | |
JPH01147546A (en) | Photomask for producing integrated circuit |