JPS63278230A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63278230A JPS63278230A JP62112968A JP11296887A JPS63278230A JP S63278230 A JPS63278230 A JP S63278230A JP 62112968 A JP62112968 A JP 62112968A JP 11296887 A JP11296887 A JP 11296887A JP S63278230 A JPS63278230 A JP S63278230A
- Authority
- JP
- Japan
- Prior art keywords
- exposure
- data
- pattern
- electron beam
- circuit part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000010894 electron beam technology Methods 0.000 claims abstract description 23
- 238000012546 transfer Methods 0.000 claims abstract description 16
- 238000013461 design Methods 0.000 claims abstract description 11
- 239000007788 liquid Substances 0.000 claims description 6
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical group CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 4
- MLFHJEHSLIIPHL-UHFFFAOYSA-N isoamyl acetate Chemical compound CC(C)CCOC(C)=O MLFHJEHSLIIPHL-UHFFFAOYSA-N 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 229940117955 isoamyl acetate Drugs 0.000 claims description 2
- 239000004793 Polystyrene Substances 0.000 claims 1
- 229920002223 polystyrene Polymers 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 21
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 9
- 238000001459 lithography Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 18
- 238000010586 diagram Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 238000003491 array Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 210000002268 wool Anatomy 0.000 description 1
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/7045—Hybrid exposures, i.e. multiple exposures of the same area using different types of exposure apparatus, e.g. combining projection, proximity, direct write, interferometric, UV, x-ray or particle beam
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Electron Beam Exposure (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
本発明の半導体ウェハのレジストパターンの形成方法は
、電子線とＤｅｅｐ−ＵＶ光の両方に感度を有するネガ
レジストを用い、ｌ１ｅｅｐ−ＵＶ光による一括転写に
よって形成する一般に設計ルールが緩和される大面積・
少品種の共通パターンと、電子線露光による直接描画に
よって形成する解像度や位置合わせ精度が要求される小
面積・多品種の特有パターンとを該ネガレジストに合成
して現像することを特徴としている。これにより、レジ
ストパターンの形成が合理的に行なわれるので、半導体
ウェハの処理効率の向上を図ることが可能となる。Detailed Description of the Invention [Summary] The method for forming a resist pattern on a semiconductor wafer of the present invention uses a negative resist that is sensitive to both electron beams and deep-UV light, and is formed by batch transfer using deep-UV light. Generally, design rules are relaxed for large areas and
It is characterized in that a common pattern for a small number of products and a unique pattern for a small number of products in a small area, which requires high resolution and alignment accuracy, formed by direct drawing using electron beam exposure, are combined into the negative resist and developed. As a result, the resist pattern can be formed in a rational manner, making it possible to improve the processing efficiency of semiconductor wafers.
本発明は半導体装置の製造方法に関するものであり、更
に詳しく言えば半導体ウェハのレジストパターンを形成
する方法に関するものである。The present invention relates to a method of manufacturing a semiconductor device, and more specifically, to a method of forming a resist pattern on a semiconductor wafer.
最近、集積回路の高密度・高集積化のため、ますます超
微細で大規模な回路パターンを形成することが要求され
ている。Recently, in order to increase the density and integration of integrated circuits, it has been required to form increasingly ultra-fine and large-scale circuit patterns.
ところで、従来高解像度を要求されない回路部のレジス
トパターンは、フォトマスクによる一括転写や数チップ
毎にレチクルによるステッパーによって形成されている
。By the way, resist patterns for circuit parts that do not require high resolution have conventionally been formed by batch transfer using a photomask or by a stepper using a reticle every few chips.
一方、高解像度を要求される回路部のレジストパターン
は、電子線露光による直接描画によって形成している・
〔発明が解決しようとする問題点〕
しかし、ウニへ全体のパターンを電子露光による直接描
画をする場合には、極めて露光時間が長くなる。特に電
源線等の幅広いパターンを描画する場合には露光スポッ
ト数も多くなる。従って、一つの半導体ウーハの処理に
ついて電子露光装置を占有する時間が長くなり量産性の
低下を招く。On the other hand, resist patterns for circuit parts that require high resolution are formed by direct drawing using electron beam exposure. In this case, the exposure time becomes extremely long. In particular, when drawing a wide pattern such as a power supply line, the number of exposure spots increases. Therefore, the time required to occupy the electronic exposure apparatus for processing one semiconductor wafer increases, resulting in a decrease in mass productivity.
また、このことからゲートアレイ等の微細大規模半導体
デバイスの作成に多大の描画時間を要するという問題が
ある。Furthermore, this also poses a problem in that a large amount of drawing time is required to create fine, large-scale semiconductor devices such as gate arrays.
本発明はかかる従来の問題に鑑み創作されたものであり
、電子線露光装置を合理的に使用して微細で大規模なデ
バイスの生産効率の向上を図る製造方法の提供を目的と
する。The present invention was created in view of such conventional problems, and aims to provide a manufacturing method that improves the production efficiency of fine and large-scale devices by rationally using an electron beam exposure apparatus.
本発明の半導体装置の製造方法は、半導体デＩ（イス設
計データから、Ｄｅｅｐ−ＵＶ光を照射して半導体ウェ
ハに一括転写をする第１の露光に要するデータと、電子
線を走査して該ウェハに直接描画をする第２の露光に要
するデータとを分離する工程と、前記第１の露光に要す
るデータから転写用マスクを形成する工程と、前記第２
の露光に要するデータからパターンデータを作成する工
程と、前記半導体ウェハの表面に、ｌ１ｓｅｐ−ＵＶ光
と電子線に感光する感光液を塗布する工程と、前記マス
クを用いて感光液を塗布した半導体の表面に対して第１
の露光をする工程と、前記パターンデータに従って前記
第１の露光をされた半導体の表面に対して重ねて第２の
露光を合成する工程と、前記第１の露光および第２の露
光をされた半導体ウェハを有機系現像液で現像する工程
とを有することを特徴とする。The method for manufacturing a semiconductor device of the present invention includes data required for first exposure in which data is transferred from semiconductor device design data to a semiconductor wafer at once by irradiating deep-UV light, and by scanning with an electron beam. a step of separating data required for the second exposure for directly writing on the wafer; a step of forming a transfer mask from the data required for the first exposure; and a step of forming the transfer mask from the data required for the first exposure.
a step of creating pattern data from the data required for exposure of the semiconductor wafer, a step of applying a photosensitive liquid sensitive to l1sep-UV light and an electron beam on the surface of the semiconductor wafer, and a step of applying the photosensitive liquid to the semiconductor wafer using the mask. The first
a step of superimposing a second exposure on the surface of the semiconductor subjected to the first exposure according to the pattern data; The method is characterized by comprising a step of developing the semiconductor wafer with an organic developer.
本発明によれば、電子線１１１ｅｅｐ −ＩＪ Ｖ光の
両方に感度を有するネガレジストを用いて、大面積少品
種ノ共通パターンをＤｅｅｐ−ＵＶ光による一括転写と
し、さらに重ねて小面積多品種の特有パターンを電子線
露光による直接描画によって合成し現像する。According to the present invention, by using a negative resist that is sensitive to both electron beam 111eep and IJ V light, a common pattern of a small number of large-area products is transferred at once using deep-UV light, and is further overlapped to transfer a common pattern of a small number of products of a small number of products. A unique pattern is synthesized and developed by direct writing using electron beam exposure.
これにより、従来に比べて電子線露光による直接描画に
要する露光面積や露光時間が短縮できる。従って、微細
大規模デバイスの製造効率が向上する。As a result, the exposure area and exposure time required for direct writing by electron beam exposure can be reduced compared to the conventional method. Therefore, the manufacturing efficiency of fine, large-scale devices is improved.
次に図を参照しながら本発明の実施例について説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の実施例に係る半導体ウーｌ＼のレジス
トパターンを形成する方法を説明する工程図である。FIG. 1 is a process diagram illustrating a method of forming a resist pattern of semiconductor wool according to an embodiment of the present invention.
まず、半導体デバイス設計データ１からＤｅｅｐ−ＵＶ
光による一括転写に必要な共通回路部データ３と、電子
線露光による直接描画に必要な微細回路部データ４とを
分離する（工程図（ａ））。First, from semiconductor device design data 1, Deep-UV
Common circuit part data 3 required for batch transfer by light and fine circuit part data 4 required for direct writing by electron beam exposure are separated (process diagram (a)).
例えば、微細ゲートアレイの設計データには、設計ルー
ルの２ｇ、ｍ以上の比較的精度が緩和される電源線、外
部入出力線およびＰＡＤ等（大面積少品種の共通回路部
データと、設計ルール２ＩＬｍ以下の厳しい精度が要求
される内部ゲートおよびユーザの希望や品種によって変
わる回路等（小面積多品種）の微細回路部データとが含
まれているので、これを分離する。For example, design data for fine gate arrays includes power supply lines, external input/output lines, PADs, etc. (common circuit data for large-area, low-volume products, and design rules for 2g, m or more, for which accuracy is relatively relaxed). This data is separated because it includes data on internal gates that require strict accuracy of 2ILm or less and microcircuits such as circuits (small area and many types) that vary depending on the user's wishes and types (small area and many types).
次に、共通回路部データ３に従ってＤｅｅｐ −Ｕ Ｖ
光による一括転写に用いるマスクを形成する（工程図（
ｂ））。Next, according to the common circuit part data 3, Deep -U V
Form a mask to be used for batch transfer using light (see process diagram (
b)).
また、微細回路部データ４に従って電子線露光による直
接描画に必要なパターンデータを作成する（工程図（Ｃ
））。In addition, pattern data necessary for direct writing by electron beam exposure is created according to the microcircuit part data 4 (process diagram (C
)).
次に、前工程を経た半導体ウェハ４の表面にネガレジス
トを塗布（厚さ１．０〜２．０ｐｍ）し、ベータ（１０
０〜２００℃、１００分）する（工程図（ｄ））。なお
、ネガレジストは電子線とｌ１ｅｅｐ−ＵＶ光の両方に
感度を有するクロロメチル化ポリエステル液を用いる。Next, a negative resist (thickness 1.0 to 2.0 pm) is applied to the surface of the semiconductor wafer 4 that has undergone the previous process, and beta (10
0 to 200°C, 100 minutes) (process diagram (d)). Note that the negative resist uses a chloromethylated polyester liquid that is sensitive to both electron beams and leep-UV light.
次いで、先に形成した転写用マスクをセットし、 （２
００〜３００ｎｍ、１〜５００ｍＪ／ｃｍ２）を照射し
て半導体ウェハのネガレジストに共通回路部パターンを
一括転写する（工程図（ｅ））。Next, set the transfer mask formed earlier, and (2
00 to 300 nm, 1 to 500 mJ/cm2) to transfer the common circuit pattern to the negative resist of the semiconductor wafer at once (process diagram (e)).
また、半導体ウェハを現像することなく、先に作成した
パターンデータに従って、続けてネガレジストに電子線
露光（１〜５０ｇＣ／ｃｍ２）により微細パターンを直
接描画する（工程図（ｆ））。Further, without developing the semiconductor wafer, a fine pattern is directly drawn on the negative resist by electron beam exposure (1 to 50 gC/cm2) according to the previously created pattern data (process diagram (f)).
次いで、一括転写および直接描画されたネガレジストを
現像する（工程図（ｇ））。なお、現像液はアセトンや
酢酸イソアミル等を用いる。Next, the batch-transferred and directly written negative resist is developed (process diagram (g)). Note that acetone, isoamyl acetate, or the like is used as the developer.
以上により半導体ウェハの共通回路部と微細回路部とを
合成したレジストパターンを形成することができる。As described above, a resist pattern can be formed in which the common circuit section and the fine circuit section of the semiconductor wafer are combined.
このようにして、本実施例によれば設計ルールの緩和さ
れる回路パターン部はｌ１ｅｅｐ−ＵＶ光による一括転
写によって形成し、設計ルールの厳しい回路パターン部
は電子線露光による直接描画によって形成し、合成して
一つの半導体デバイスのレジストパターンを形成するこ
とができる。これにより、一つの半導体ウェハの電子線
露光による直接描画処理に要する露光面積および露光時
間を短縮することができる。In this way, according to this embodiment, the circuit pattern part with relaxed design rules is formed by batch transfer using l1eep-UV light, and the circuit pattern part with strict design rules is formed by direct drawing with electron beam exposure. A resist pattern for one semiconductor device can be formed by combining the resist patterns. This makes it possible to shorten the exposure area and exposure time required for direct writing processing using electron beam exposure on one semiconductor wafer.
特に共通回路部分を含み多品種の回路を生成するゲート
アレイ等に適用すればその効果が大きい。この場合には
、各回路に共通で大面積の電源線パターン等はＤｅｅｐ
−ＩＪ ｙ光で一括転写して形成し、−劣者回路特有
のパターンあるいは微細パターンのみを電子線装置によ
り形成する。The effect is particularly great when applied to gate arrays and the like that generate a wide variety of circuits including common circuit parts. In this case, the large-area power line pattern common to each circuit should be deep
- It is formed by batch transfer using IJy light, and - Only a pattern specific to the inferior circuit or a fine pattern is formed using an electron beam device.
以上説明したように、本発明によれば共通ネガレストを
用いて、大面積少品種の回路パターンと小面積多品種の
回路パターンを合成する。これにより、一つの半導体ウ
ーハの電子線による直接描画の処理時間が短縮し、該露
光装置の占有時間が短くなるので量産性が向上する。As described above, according to the present invention, a common negative rest is used to synthesize a circuit pattern with a large area and a small number of types and a circuit pattern with a small area and a large number of types. As a result, the processing time for direct drawing of one semiconductor wafer with an electron beam is shortened, and the time occupied by the exposure apparatus is shortened, so that mass productivity is improved.
特に共通パターンを含むゲートアレイ等に適用すればそ
の効果は大きい。The effect is particularly great when applied to a gate array or the like that includes a common pattern.
第１図は本発明の実施例に係る半導体ウーハのレジスト
パターンを形成する方法を説明する工程図である。
（符号の説明）
ａ・・・設計データ分離工程、
ｂ・・・転写用マスク形成工程、
Ｃ・・・パターンデータ作成工程、
ｄ・・・塗布工程、
ｅ・・・第１の露光をする工程、
ｆ・・・第２の露光をする工程、
ｇ・・・現像工程、
ｌ・・・半導体デバイス設計データ、
２・・・第１の露光（Ｄｅｅｐ−ＵＶ光による一括転写
）に要するデータ、
３・・・第２の露光（電子線による直接描画）に要する
データ、
４・・・半導体ウェハ、
５・・・レジストパターンーFIG. 1 is a process diagram illustrating a method of forming a resist pattern for a semiconductor wafer according to an embodiment of the present invention. (Explanation of symbols) a...Design data separation process, b...Transfer mask formation process, C...pattern data creation process, d...coating process, e...first exposure Step, f...Process of second exposure, g...Development process, l...Semiconductor device design data, 2...Data required for first exposure (batch transfer using Deep-UV light) , 3...Data required for second exposure (direct writing with electron beam), 4...Semiconductor wafer, 5...Resist pattern-
Claims (2)
光を照射して半導体ウェハに一括転写をする第１の露光
に要するデータと、電子線を走査して該ウェハに直接描
画をする第２の露光に要するデータとを分離する工程と
、 前記第１の露光に要するデータから転写用マスクを形成
する工程と、 前記第２の露光に要するデータからパターンデータを作
成する工程と、 前記半導体ウェハの表面に、Ｄｅｅｐ−ＵＶ光と電子線
とに感光する感光液を塗布する工程と、前記マスクを用
いて感光液を塗布した半導体の表面に対して第１の露光
をする工程と、 前記パターンデータに従って前記第１の露光をされた半
導体の表面に対して重ねて第２の露光を合成する工程と
、 前記第１の露光および第２の露光をされた半導体ウェハ
を有機系の現像液で現像する工程とを有することを特徴
とする半導体装置の製造方法。(1) Deep-UV from semiconductor device design data
a step of separating data required for a first exposure, in which data is collectively transferred onto a semiconductor wafer by irradiating light, and data required for a second exposure, in which writing is directly performed on the wafer by scanning an electron beam; forming a transfer mask from the data required for the first exposure; creating pattern data from the data required for the second exposure; and exposing the surface of the semiconductor wafer to deep-UV light and an electron beam. applying a photosensitive liquid to the surface of the semiconductor coated with the photosensitive liquid using the mask; A semiconductor device characterized by comprising: a step of superimposing a second exposure on the first and second exposures, and a step of developing the semiconductor wafer subjected to the first exposure and the second exposure with an organic developer. Production method.
り、有機系の現像液がアセトンまたは酢酸イソアミルで
あることを特徴とする特許請求の範囲第１項に記載の半
導体装置の製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the photosensitive liquid is chloromethylated polystyrene, and the organic developer is acetone or isoamyl acetate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62112968A JPS63278230A (en) | 1987-05-09 | 1987-05-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62112968A JPS63278230A (en) | 1987-05-09 | 1987-05-09 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63278230A true JPS63278230A (en) | 1988-11-15 |
Family
ID=14600055
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62112968A Pending JPS63278230A (en) | 1987-05-09 | 1987-05-09 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63278230A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH097924A (en) * | 1995-06-21 | 1997-01-10 | Nec Corp | Equipment and method for manufacturing semiconductor device |
| JPH10189415A (en) * | 1996-12-26 | 1998-07-21 | Hitachi Ltd | Method and device for forming resist pattern |
| JP2002110534A (en) * | 2000-10-03 | 2002-04-12 | Advantest Corp | Semiconductor element manufacturing system and electron beam aligner |
| JP2011176046A (en) * | 2010-02-23 | 2011-09-08 | Fujitsu Semiconductor Ltd | Exposure method and method of making semiconductor device |
| JP2012028555A (en) * | 2010-07-23 | 2012-02-09 | Fujitsu Semiconductor Ltd | Exposure data creation method, exposure data creating device, and semiconductor device manufacturing method |
-
1987
- 1987-05-09 JP JP62112968A patent/JPS63278230A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH097924A (en) * | 1995-06-21 | 1997-01-10 | Nec Corp | Equipment and method for manufacturing semiconductor device |
| JPH10189415A (en) * | 1996-12-26 | 1998-07-21 | Hitachi Ltd | Method and device for forming resist pattern |
| JP2002110534A (en) * | 2000-10-03 | 2002-04-12 | Advantest Corp | Semiconductor element manufacturing system and electron beam aligner |
| JP2011176046A (en) * | 2010-02-23 | 2011-09-08 | Fujitsu Semiconductor Ltd | Exposure method and method of making semiconductor device |
| JP2012028555A (en) * | 2010-07-23 | 2012-02-09 | Fujitsu Semiconductor Ltd | Exposure data creation method, exposure data creating device, and semiconductor device manufacturing method |
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