CN116859665A - Mask and wafer exposure method - Google Patents

Mask and wafer exposure method Download PDF

Info

Publication number
CN116859665A
CN116859665A CN202310872604.4A CN202310872604A CN116859665A CN 116859665 A CN116859665 A CN 116859665A CN 202310872604 A CN202310872604 A CN 202310872604A CN 116859665 A CN116859665 A CN 116859665A
Authority
CN
China
Prior art keywords
area
mask
exposure
monitoring
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310872604.4A
Other languages
Chinese (zh)
Inventor
姜清华
高谷信一郎
李新宇
丁帼君
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changzhou Chengxin Semiconductor Co Ltd
Original Assignee
Changzhou Chengxin Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changzhou Chengxin Semiconductor Co Ltd filed Critical Changzhou Chengxin Semiconductor Co Ltd
Priority to CN202310872604.4A priority Critical patent/CN116859665A/en
Publication of CN116859665A publication Critical patent/CN116859665A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/76—Patterning of masks by imaging
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/80—Etching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70691—Handling of masks or workpieces

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

A mask and a wafer exposure method, wherein the exposure method comprises the following steps: providing a wafer, wherein the wafer is correspondingly provided with a plurality of exposure areas; providing an original mask, wherein the original mask comprises a public area, a supplement area and a monitoring area, and a mask pattern of the monitoring area is used for forming a process control monitoring structure in the wafer; and performing successive exposure processing on each exposure area, and during the exposure processing, performing exposure processing on part of the exposure areas based on the monitoring area. In the exposure process, the exposure treatment is performed in part of the exposure area based on the monitoring area, so that the number of structures for process control monitoring formed in the wafer is reduced, the area for forming actual shipment chips is further reduced, and the chip output number of the wafer is increased.

Description

Mask and wafer exposure method
Technical Field
The invention relates to the technical field of semiconductors, in particular to a mask and a wafer exposure method.
Background
An integrated circuit is formed by forming semiconductor devices on the surface of a silicon wafer in the range of a few microns, and then interconnecting the devices through metal interconnect lines. With the development of semiconductor technology, in order to improve product performance and save cost, the density of integrated circuits is increasing and the feature size is decreasing. Among them, photolithography and exposure processes take a significant role in semiconductor processes.
In the manufacturing process of a semiconductor device, patterning of each layer of film and ion implantation of the semiconductor are defined by photolithography, and the specific steps include: and spin-coating photoresist on the surface of the wafer to form a photoresist layer, and then exposing and developing the photoresist layer to transfer the pattern on the mask plate to the photoresist layer on the surface of the wafer.
The steps of performing the exposure process generally include: dividing the wafer into a plurality of exposure units, moving the wafer to enable each exposure unit to sequentially pass through an exposure field, and completing exposure of each exposure unit until the exposure of the whole wafer is completed.
However, the existing wafer exposure method has a plurality of problems.
Disclosure of Invention
The invention solves the technical problem of providing a mask and an exposure method of a wafer so as to increase the chip output quantity of the wafer.
In order to solve the above problems, the present invention provides an exposure method for a wafer, comprising: providing a wafer, wherein the wafer is correspondingly provided with a plurality of exposure areas; providing an original mask, wherein the original mask comprises a public area, a supplement area and a monitoring area, and a mask pattern of the monitoring area is used for forming a process control monitoring structure in the wafer; and performing successive exposure processing on each exposure area, and during the exposure processing, performing exposure processing on part of the exposure areas based on the monitoring area.
Optionally, before performing the successive exposure processing on each exposure area, the method further includes: and acquiring a conventional mask and a monitoring mask based on the original mask, wherein the conventional mask comprises the public area and the supplementary area, and the monitoring mask comprises the public area and the monitoring area.
Optionally, the method for exposing a part of the exposure area based on the monitoring area includes: and performing exposure processing on part of the exposure area based on the monitoring mask.
Optionally, the common area, the supplementary area and the monitoring area are arranged along a first direction, and the common area is located between the supplementary area and the monitoring area.
Optionally, the method for acquiring the conventional mask and the monitoring mask based on the original mask includes: and in the exposure processing process, shielding the monitoring area in the original mask plate to obtain the conventional mask plate, and shielding the supplementary area in the original mask plate to obtain the monitoring mask plate.
Optionally, the common area, the supplementary area and the monitoring area are arranged along a first direction, and the common area includes: a first sub-common area and a second sub-common area, the monitoring area is located between the first sub-common area and the second sub-common area, and the supplementary area is adjacent to the first sub-common area or the second sub-common area.
Optionally, obtaining the conventional mask includes: and obtaining a first split mask and a second split mask.
Optionally, the method for acquiring the conventional mask and the monitoring mask based on the original mask includes: in the exposure processing process, the monitoring area, the first sub-public area and the supplementary area in the original mask are shielded, the first split mask is obtained, the monitoring area and the second sub-public area in the original mask are shielded, the second split mask is obtained, and the supplementary area in the original mask is shielded, so that the monitoring mask is obtained.
Optionally, the area of the monitoring area is smaller than the area of the exposure area.
Optionally, the wafer includes: the device comprises a central area and a plurality of edge areas, wherein the plurality of edge areas are distributed on the periphery of the central area.
Optionally, when the exposure processing is performed on the exposure areas corresponding to the central area and the edge area of the wafer, the monitoring mask is based.
Correspondingly, the technical scheme of the invention also provides a mask plate, which comprises the following steps: the mask pattern of the monitoring area is used for forming a process control and monitoring structure in the wafer; and in the exposure process, the part of the exposure area corresponding to the wafer is subjected to exposure processing based on the monitoring area.
Optionally, the common area, the supplementary area and the monitoring area are arranged along a first direction, and the common area is located between the supplementary area and the monitoring area.
Optionally, the common area, the supplementary area and the monitoring area are arranged along a first direction, and the common area includes: a first sub-common area and a second sub-common area, the monitoring area is located between the first sub-common area and the second sub-common area, and the supplementary area is adjacent to the first sub-common area or the second sub-common area.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the exposure method of the wafer in the technical scheme of the invention, in the exposure process, the exposure treatment is carried out on part of the exposure area based on the monitoring area so as to reduce the number of structures for forming process control monitoring in the wafer, thereby reducing the area for forming actual shipment chips and increasing the chip output number of the wafer.
Further, the common area, the supplemental area and the monitoring area are arranged along a first direction, the common area being located between the supplemental area and the monitoring area; the method for acquiring the conventional mask and the monitoring mask based on the original mask comprises the following steps: and in the exposure processing process, shielding the monitoring area in the original mask plate to obtain the conventional mask plate, and shielding the supplementary area in the original mask plate to obtain the monitoring mask plate. Because the supplemental area is adjacent to and continuous with the public area, the conventional mask can be obtained by only carrying out one-time shielding exposure on the original mask, and the exposure efficiency is effectively improved.
In the mask plate of the technical scheme of the invention, the mask plate comprises: the mask pattern of the monitoring area is used for forming a process control and monitoring structure in the wafer; in the exposure process, the partial exposure area corresponding to the wafer is subjected to exposure treatment based on the monitoring area so as to reduce the number of structures for forming process control monitoring in the wafer, thereby reducing the area occupied by forming actual shipment chips and increasing the chip output quantity of the wafer.
Further, the common area, the supplemental area and the monitoring area are arranged along a first direction, the common area being located between the supplemental area and the monitoring area. Because the supplemental area is adjacent to and continuous with the public area, the conventional mask can be obtained by only carrying out one-time shielding exposure on the mask, and the exposure efficiency is effectively improved.
Drawings
FIG. 1 is a schematic view of a wafer exposure mode;
FIG. 2 is a flow chart of a method for exposing a wafer according to an embodiment of the invention;
fig. 3 to 6 are schematic structural views of steps of an exposure method for a wafer according to an embodiment of the invention;
FIG. 7 is a schematic view of an original mask in another embodiment of the present invention;
fig. 8 is a schematic structural diagram of obtaining a first split mask, a second split mask, and a monitor mask according to another embodiment of the present invention.
Detailed Description
As described in the background, there are many problems associated with the wafer exposure method. The following will make a detailed description with reference to the accompanying drawings.
Fig. 1 is a schematic view of an exposure pattern of a wafer.
Referring to fig. 1, in the present exposure mode, each exposure area 100 (shot) has a certain process control monitor (Process Control Monitor, PCM) area 101, and according to the step-by-step exposure mode of the exposure area 100, how many times a wafer 102 is exposed forms how many process control monitor areas 101.
However, the monitoring of the wafer 102 generally only requires testing for process control monitoring at the center and at several edge locations of the wafer 102 to reflect the process conditions of the entire wafer 102. Therefore, forming the process control and monitoring area 101 in each exposure area 100 occupies the area where the shipment chips are formed, thereby severely affecting the number of chips produced on the wafer 102.
On the basis, the invention provides a mask and a wafer exposure method, wherein in the exposure process, the number of structures for process control monitoring formed in the wafer is reduced by carrying out exposure treatment on part of the exposure area based on the monitoring area, so that the area for forming actual shipment chips is reduced, and the chip output quantity of the wafer is increased.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 2 is a flow chart of an exposure method of a wafer according to an embodiment of the invention, including:
step S101, providing a wafer, wherein the wafer is provided with a plurality of exposure areas correspondingly;
step S102, providing an original mask, wherein the original mask comprises a public area, a supplement area and a monitoring area, and a mask pattern of the monitoring area is used for forming a process control and monitoring structure in the wafer;
step S103, performing successive exposure processing on each exposure area, and during the exposure processing, performing exposure processing on a part of the exposure areas based on the monitoring area.
The steps of the mask layout forming method will be described in detail with reference to the accompanying drawings.
Fig. 3 to 6 are schematic structural views of steps of an exposure method for a wafer according to an embodiment of the invention; FIG. 7 is a schematic view of an original mask in another embodiment of the present invention; fig. 8 is a schematic structural diagram of obtaining a first split mask, a second split mask, and a monitor mask according to another embodiment of the present invention.
Referring to fig. 3, a wafer 200 is provided, and the wafer 200 has a plurality of exposure areas 400.
In this embodiment, the exposure area 400 is an area that can be supported by a single exposure implementation of the lithography machine in the lithography process.
In this embodiment, the wafer 200 has a plurality of chip regions (not shown).
In this embodiment, each of the chip regions is configured to form a specific chip structure, wherein a portion of the chip structure formed by the chip region is used as an actual shipment chip and another portion of the chip structure formed by the chip region is used for process control monitoring (Process Control Monitor, PCM).
In this embodiment, during the exposure process, each exposure area 400 can form a corresponding mask pattern on a plurality of chip areas.
In a specific example, if the size of the wafer 200 is 6 inches, the chip area with the calculated reference being 5mm inward from the edge of the wafer 200 may form an effective chip that can be shipped, the size of the chip area is 0.2mm x 0.2mm, and the size of each exposure area 400 is 20mm x 19.8mm, so that the overall area formed by each exposure area 400 can cover the area of the wafer, and the exposure areas 400 also need to be arranged in an array, and the whole wafer 200 needs to correspond to 8 x 8 exposure areas 400.
With continued reference to fig. 3, in this embodiment, the wafer 200 includes: the device comprises a central area I and a plurality of edge areas II, wherein the plurality of edge areas II are distributed on the periphery of the central area I.
In this embodiment, the central area I and the plurality of edge areas II are uniformly distributed at each position of the wafer 200, and then a process control monitoring structure is formed in the central area I and a part of the chip areas in the plurality of edge areas I, so that the process can be monitored more comprehensively and reliably.
In this embodiment, the number of the edge areas II is 4; in other embodiments, the number of the edge regions may be 8 or 12.
Referring to fig. 4, an original mask 300 is provided, where the original mask 300 includes a common area 301, a supplemental area 302, and a monitor area 303, and a mask pattern of the monitor area 303 is used to form a process control monitor structure in the wafer 200.
In this embodiment, the common area 301, the supplementary area 302 and the monitoring area 303 are arranged along the first direction X, and the common area 301 is located between the supplementary area 302 and the monitoring area 303.
Referring to fig. 7, in other embodiments, the common area 301, the supplementary area 302, and the monitoring area 303 are arranged along a first direction X, and the common area 301 includes: a first sub-common area 3011 and a second sub-common area 3012, the monitor area 303 is located between the first sub-common area 3011 and the second sub-common area 3012, and the supplementary area 302 is adjacent to the first sub-common area 3011 or the second sub-common area 3012.
In this embodiment, the area of the monitor area 303 is an integer multiple of the area of the chip area, so as to ensure that a structure for subsequent process control and monitor can be formed on the complete chip area, thereby avoiding that only a part of the chip area forms a structure for process control and monitor, further causing waste of the chip area and reducing the number of actual shipment chips.
In this embodiment, the area of the monitor area 303 is smaller than the area of the exposure area 400.
Referring to fig. 5, a conventional mask 300A and a monitor mask 300B are obtained based on the original mask 300, wherein the conventional mask 300A includes the common area 301 and the supplementary area 302, and the monitor mask 300B includes the common area 301 and the monitor area 303.
In this embodiment, the method for obtaining the conventional reticle 300A and the monitoring reticle 300B based on the original reticle 300 includes: during the exposure process, the monitoring area 303 in the original mask 300 is blocked, the normal mask 300A is obtained, and the supplementary area 302 in the original mask 300 is blocked, so that the monitoring mask 300B is obtained.
In this embodiment, since the supplemental area 302 is adjacent to and continuous with the common area 301, the conventional mask 300A can be obtained by performing the shielding exposure on the original mask 300 only once, which effectively improves the exposure efficiency.
Referring to fig. 8, in other embodiments, when the common area 301, the supplementary area 302, and the monitoring area 303 are arranged along the first direction X, the common area 301 includes: the monitoring area 303 is located between the first sub-common area 3011 and the second sub-common area 3012, and when the supplemental area 302 is adjacent to the first sub-common area 3011 or the second sub-common area 3012, the obtaining the conventional reticle 300A includes: a first split reticle 300Aa is acquired and a second split reticle 300Ab is acquired.
The method for obtaining the conventional mask 300A and the monitoring mask 300B based on the original mask 300 includes: in the exposure process, the monitoring area 303, the first sub-common area 3011 and the supplementary area 302 in the original mask 300 are shielded, the first split mask 300Aa is obtained, the monitoring area 303 and the second sub-common area 3012 in the original mask 300 are shielded, the second split mask 300Ab is obtained, and the supplementary area 302 in the original mask 300 is shielded, so as to obtain the monitoring mask 300B.
It should be noted that, in the exposure process, the continuity of the subsequent exposure pattern needs to be considered in the first split mask 300Aa and the second split mask 300Ab. Specifically, after the exposure of the first split mask 300Aa and before the exposure of the second split mask 300Ab, the position of the second split mask 300Ab is adjusted to ensure that the exposed pattern and the exposed pattern of the first split mask 300Aa remain continuous.
Referring to fig. 6, each exposure area 400 is subjected to successive exposure processing, and during the exposure processing, a part of the exposure area 400 is subjected to exposure processing based on the monitor area 303.
In this embodiment, during the exposure process, an exposure process is performed in a portion of the exposure area 400 based on the monitor area 303, so as to reduce the number of structures for forming process control monitor in the wafer 200, and further reduce the area occupied by forming actual shipment chips, so as to increase the chip yield of the wafer 200.
In this embodiment, the method for performing the exposure processing on a part of the exposure area 400 based on the monitor area 303 includes: and performing exposure processing on a part of the exposure area 400 based on the monitoring mask 300B.
In this embodiment, the monitoring mask 300B is used for performing exposure processing on the central region I and the edge region II of the wafer 200.
Continuing with the above specific example, taking the size of the wafer 200 as 6 inches, calculating the reference to be that the chip area within 5mm from the edge of the wafer 200 can form an effective chip that can be shipped, where the size of the chip area is 0.2mm by 0.2mm, the size of each exposure area 400 is 20mm by 19.8mm, the size of each monitor area 303 is 20mm by 0.2mm, and the entire wafer 200 needs to correspond to 8 by 8 exposure areas 400, where the process monitor control structure is formed in 5 exposure areas 400.
The number of chips that each of the regular reticles 300A can form an effective shipment is 100×99, and the number of chips that each of the monitor reticles 300B can form an effective shipment is 100×98 because the 100×1 chip structures formed by the monitor areas are used for process monitoring control in each of the monitor reticles 300B.
If the process monitoring control structure is formed with all of the exposure areas 400 at present, the number of actual shipment chips formed is 429437. If the process monitoring control structure is formed by using part of the exposure area 400 in this embodiment, the number of the formed actual shipment chips is 439768, and 10331 actual shipment chips are added, and the adding ratio is 2.4%.
In this embodiment, the apparatus for performing a line-by-line exposure process on the wafer 200 includes: a stepper or a scanning lithography machine.
It should be noted that, in this embodiment, the stepper and the scanning lithography machine use one exposure area 400 as one mask, and if the masks required for each exposure area 400 are the same in the whole exposure process, only one mask is required in the whole exposure process; if a different mask is required for the exposure area 400 (e.g., the mask with the monitor area 303 in the embodiment) during the whole exposure process, the mask is adjusted to cover the original mask 300.
Correspondingly, in an embodiment of the present invention, a mask is further provided, please continue to refer to fig. 4, including: a common region 301, a supplemental region 302, and a monitor region 303, wherein the mask pattern of the monitor region 303 is used to form a process control monitor structure in the wafer 200; in the exposure process, the exposure area 400 corresponding to the wafer 200 is exposed based on the monitor area 303.
In this embodiment, during the exposure process, the mask may be subjected to shielding regulation, so that a part of the exposure area 400 is subjected to exposure processing based on the conventional mask 300A without the monitor area 303, another part of the exposure area 400 is subjected to exposure processing based on the monitor mask 300B with the monitor area 303, so as to reduce the number of structures forming process control monitoring in the wafer 200, and further reduce the area occupied for forming actual shipment chips, so as to increase the chip yield number of the wafer 200
With continued reference to fig. 5, in this embodiment, the common area 301, the supplemental area 302 and the monitoring area 303 are arranged along a first direction X, and the common area 301 is located between the supplemental area 302 and the monitoring area 303. Because the supplemental area 302 is adjacent to and continuous with the common area 301, the conventional mask 300A can be obtained by performing one-time shielding exposure on the mask, and the exposure efficiency is effectively improved.
With continued reference to fig. 7, in other embodiments, the common area 301, the supplemental area 302, and the monitoring area 303 are arranged along a first direction X, and the common area 301 includes: a first sub-common area 3011 and a second sub-common area 3012, the monitor area 303 is located between the first sub-common area 3011 and the second sub-common area 3012, and the supplementary area 302 is adjacent to the first sub-common area 3011 or the second sub-common area 3012.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (14)

1. A method for exposing a wafer, comprising:
providing a wafer, wherein the wafer is correspondingly provided with a plurality of exposure areas;
providing an original mask, wherein the original mask comprises a public area, a supplement area and a monitoring area, and a mask pattern of the monitoring area is used for forming a process control monitoring structure in the wafer;
and performing successive exposure processing on each exposure area, and during the exposure processing, performing exposure processing on part of the exposure areas based on the monitoring area.
2. The method of exposing a wafer according to claim 1, further comprising, before subjecting each of the exposure areas to successive exposure processing: and acquiring a conventional mask and a monitoring mask based on the original mask, wherein the conventional mask comprises the public area and the supplementary area, and the monitoring mask comprises the public area and the monitoring area.
3. The method of exposing a wafer according to claim 2, wherein the method of exposing a part of the exposed area based on the monitor area comprises: and performing exposure processing on part of the exposure area based on the monitoring mask.
4. The method of exposing a wafer according to claim 2, wherein the common area, the supplemental area, and the monitor area are arranged along a first direction, the common area being located between the supplemental area and the monitor area.
5. The method of exposing a wafer according to claim 4, wherein the method of obtaining the regular reticle and the monitor reticle based on the original reticle comprises: and in the exposure processing process, shielding the monitoring area in the original mask plate to obtain the conventional mask plate, and shielding the supplementary area in the original mask plate to obtain the monitoring mask plate.
6. The method of exposing a wafer according to claim 2, wherein the common area, the supplemental area, and the monitor area are arranged along a first direction, the common area including: a first sub-common area and a second sub-common area, the monitoring area is located between the first sub-common area and the second sub-common area, and the supplementary area is adjacent to the first sub-common area or the second sub-common area.
7. The method of exposing a wafer according to claim 6, wherein obtaining the conventional reticle comprises: and obtaining a first split mask and a second split mask.
8. The method of exposing a wafer according to claim 7, wherein the method of acquiring the regular reticle and the monitor reticle based on the original reticle comprises: in the exposure processing process, the monitoring area, the first sub-public area and the supplementary area in the original mask are shielded, the first split mask is obtained, the monitoring area and the second sub-public area in the original mask are shielded, the second split mask is obtained, and the supplementary area in the original mask is shielded, so that the monitoring mask is obtained.
9. The method of exposing a wafer according to claim 1, wherein the area of the monitor region is smaller than the area of the exposure region.
10. The method of exposing a wafer according to claim 3, wherein the wafer comprises: the device comprises a central area and a plurality of edge areas, wherein the plurality of edge areas are distributed on the periphery of the central area.
11. The method according to claim 10, wherein the monitoring mask is used for performing exposure processing on the exposure regions corresponding to the center region and the edge region of the wafer.
12. A reticle, comprising:
the mask pattern of the monitoring area is used for forming a process control and monitoring structure in the wafer;
and in the exposure process, the part of the exposure area corresponding to the wafer is subjected to exposure processing based on the monitoring area.
13. The reticle of claim 12, wherein the common zone, the supplemental zone, and the monitor zone are arranged along a first direction, the common zone being located between the supplemental zone and the monitor zone.
14. The reticle of claim 12, wherein the common zone, the supplemental zone, and the monitor zone are arranged along a first direction, the common zone comprising: a first sub-common area and a second sub-common area, the monitoring area is located between the first sub-common area and the second sub-common area, and the supplementary area is adjacent to the first sub-common area or the second sub-common area.
CN202310872604.4A 2023-07-14 2023-07-14 Mask and wafer exposure method Pending CN116859665A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310872604.4A CN116859665A (en) 2023-07-14 2023-07-14 Mask and wafer exposure method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310872604.4A CN116859665A (en) 2023-07-14 2023-07-14 Mask and wafer exposure method

Publications (1)

Publication Number Publication Date
CN116859665A true CN116859665A (en) 2023-10-10

Family

ID=88235689

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310872604.4A Pending CN116859665A (en) 2023-07-14 2023-07-14 Mask and wafer exposure method

Country Status (1)

Country Link
CN (1) CN116859665A (en)

Similar Documents

Publication Publication Date Title
TWI413160B (en) Semiconductor lithography process
CN100536091C (en) Double exposure double resist layer process for forming gate patterns
US7569309B2 (en) Gate critical dimension variation by use of ghost features
US6218089B1 (en) Photolithographic method
CN110716386B (en) Optical proximity effect correction method, optical proximity effect correction device and mask
TWI235415B (en) Method and device for improving uniformity of critical dimension between different patterns of semiconductor devices
CN113495424B (en) Optical proximity correction method and mask manufacturing method
JP2002202585A5 (en)
JP2002202585A (en) Method of manufacturing photomask and method of manufacturing semiconductor integrated circuit device
US5885756A (en) Methods of patterning a semiconductor wafer having an active region and a peripheral region, and patterned wafers formed thereby
CN116859665A (en) Mask and wafer exposure method
CN112824972A (en) Target layout and mask layout correction method, mask and semiconductor structure
JP2004071650A (en) Exposure method
CN116339065A (en) Graph correction method
JPS63278230A (en) Manufacture of semiconductor device
CN114063380A (en) Pattern correction method and method for forming semiconductor structure
JPH1064779A (en) Manufacture of semiconductor device and semiconductor manufacturing apparatus for use therewith
US20100310972A1 (en) Performing double exposure photolithography using a single reticle
JPH0651496A (en) Mask for production of semiconductor integrated circuit
JP2715462B2 (en) Reticle and method of manufacturing semiconductor device using the same
CN118534717A (en) Optical proximity correction method
JPH09283413A (en) Exposure method and aligner
JPS6254921A (en) Manufacture of semiconductor device
JPS60221757A (en) Mask for exposure
JPH07181686A (en) Forming method of resist pattern

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination