JPH097924A - Equipment and method for manufacturing semiconductor device - Google Patents
Equipment and method for manufacturing semiconductor deviceInfo
- Publication number
- JPH097924A JPH097924A JP7153734A JP15373495A JPH097924A JP H097924 A JPH097924 A JP H097924A JP 7153734 A JP7153734 A JP 7153734A JP 15373495 A JP15373495 A JP 15373495A JP H097924 A JPH097924 A JP H097924A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- electron beam
- ultraviolet light
- far
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/7045—Hybrid exposures, i.e. multiple exposures of the same area using different types of exposure apparatus, e.g. combining projection, proximity, direct write, interferometric, UV, x-ray or particle beam
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Electron Beam Exposure (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造装置及
び半導体装置の製造方法に関し、特にゲートアレイ等の
少量生産製品のパターン形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing apparatus and a semiconductor device manufacturing method, and more particularly to a pattern forming method for a small-volume production product such as a gate array.
【０００２】[0002]
【従来の技術】従来、ゲートアレイやマスクロム等の少
量多品種製品の製造方法においては、品種毎に独立に製
造を行うと生産性が極めて低下することから以下に示す
ような製造方法がとられている。2. Description of the Related Art Conventionally, in a method for manufacturing a small amount of a wide variety of products such as a gate array and a mask chrome, the following manufacturing method is adopted because the productivity is extremely reduced if each product is manufactured independently. ing.
【０００３】すなわち、上記のような製品の製造工程に
おいては、回路の配線パターンの転写工程に用いるレテ
ィクル（Ｒｅｔｉｃｌｅ：ガラスマスクの一種）が品種
毎に異なる以外は全く同一の製造工程を経る。That is, in the manufacturing process of the product as described above, the manufacturing process is exactly the same except that the reticle (a kind of glass mask) used in the transfer process of the wiring pattern of the circuit is different for each kind.
【０００４】そのため、この製造工程では、図６に示す
ように、成膜工程（図６の工程Ｓ２１）の後に行われる
配線工程において、配線パターンを形成するための感光
性有機材料を塗布して感光性有機材料被膜を形成する工
程（図６の工程Ｓ２２）の後または前にロットの分割
（図６の工程Ｓ２３）を行っている。Therefore, in this manufacturing process, as shown in FIG. 6, a photosensitive organic material for forming a wiring pattern is applied in a wiring process performed after the film forming process (process S21 in FIG. 6). Lot division (step S23 in FIG. 6) is performed after or before the step (step S22 in FIG. 6) of forming the photosensitive organic material film.
【０００５】これら分割された各ロットに対しては各々
異なる露光装置を用いて露光を行うか、あるいは同一の
露光装置で順次レティクルを交換して露光を行っている
（図６の工程Ｓ２４〜Ｓ２６）。Each of these divided lots is exposed by using different exposure apparatuses, or exposure is performed by sequentially exchanging reticles by the same exposure apparatus (steps S24 to S26 in FIG. 6). ).
【０００６】これらの露光後に、各ロットの統合（図６
の工程Ｓ２７）を行ってから現像（図６の工程Ｓ２８）
及びエッチング（図６の工程Ｓ２９）が行われる。尚、
各ロット毎に現像を行ってから各ロットの統合を行う方
法もある。After these exposures, the lots are integrated (see FIG. 6).
Step S27) and then development (Step S28 in FIG. 6)
And etching (step S29 in FIG. 6) are performed. still,
There is also a method of performing development for each lot and then integrating the lots.
【０００７】一般に、露光装置にレティクルを設置して
露光可能状態にするためにはペリクル（Ｐｅｌｌｉｃｌ
ｅ）でレティクル上に樹脂の薄膜を形成してレティクル
上のゴミによる露光工程への影響を除去し、レティクル
上のゴミ検査を不要とした場合でも５分以上の時間を必
要とする。また、ペリクルを用いない場合においては１
５分以上の時間を必要とする。Generally, a pellicle (Pellicl) is used to set a reticle in an exposure apparatus so that the reticle can be exposed.
In step e), a resin thin film is formed on the reticle to remove the influence of dust on the reticle on the exposure process. Even if the dust inspection on the reticle is unnecessary, it takes 5 minutes or more. When the pellicle is not used, 1
Requires more than 5 minutes.
【０００８】この場合、少量多品種製品においては一枚
のレティクル当たりの製品の生産量が少ないため、露光
可能状態とするまでの時間を短縮するためにペリクルを
用いるとコストが非常に高くなってしまう。In this case, in the case of a small amount of a wide variety of products, since the production amount of a product per reticle is small, the cost becomes very high if the pellicle is used to shorten the time until the exposure becomes possible. I will end up.
【０００９】このため、少量多品種製品のリソグラフィ
工程では最近、電子線描画装置による半導体基板への直
接描画が検討されている。電子線描画装置による半導体
基板への直接描画ではレティクルを使用しないためにレ
ティクル作成に要する時間及び費用を削減することがで
き、またレティクルを露光装置に設置することによる生
産性の低下も発生しない。Therefore, in the lithography process for a small amount of a wide variety of products, direct drawing on a semiconductor substrate by an electron beam drawing apparatus has recently been studied. Since the reticle is not used in the direct drawing on the semiconductor substrate by the electron beam drawing apparatus, the time and cost required for making the reticle can be reduced, and the productivity is not reduced by installing the reticle in the exposure apparatus.
【００１０】[0010]
【発明が解決しようとする課題】上述した従来の少量多
品種製品の製造方法では、回路中の僅かな部分のみ異な
った多数の品種を製造する場合、露光工程の前後で製造
ロットの分割及び統合を行っているので、少量多品種製
品を製造するために多数のレティクルを必要とし、それ
らレティクルを製造するために多額の費用が必要とな
る。According to the above-described conventional method for manufacturing a small amount of a large variety of products, when a large number of different types of products are manufactured in which only a small part of the circuit is manufactured, the production lots are divided and integrated before and after the exposure process. Therefore, a large number of reticles are required to manufacture a small amount of a wide variety of products, and a large amount of cost is required to manufacture those reticles.
【００１１】また、露光装置では分割された各ロット毎
にレティクルを設置して露光可能状態としなければなら
ないので、各ロット毎にレティクルの設置と露光とを行
わなければならず、露光装置の生産性が著しく悪化して
しまう。Further, in the exposure apparatus, a reticle must be set for each divided lot so that the lot can be exposed. Therefore, the reticle must be set and exposed for each lot. The sex will deteriorate significantly.
【００１２】一方、電子線描画装置を用いて半導体基板
に直接描画する場合にはレティクルを使用しないため、
レティクル作成に要する時間及び費用を削減することが
できるが、半導体基板個々に対して描画を行わなければ
ならないので、光による一括露光に比してスループット
が極めて悪くなり、８インチウェハを用いた場合には７
〜８枚／時間程度であり、半導体装置製造における生産
性の改善を見込むことができない。On the other hand, since the reticle is not used when writing directly on the semiconductor substrate using the electron beam writing apparatus,
Although it is possible to reduce the time and cost required to create a reticle, since the writing must be performed on each semiconductor substrate, the throughput is much worse than the batch exposure by light, and when an 8-inch wafer is used. To 7
It is about 8 sheets / hour, and it cannot be expected to improve productivity in semiconductor device manufacturing.
【００１３】そこで、本発明の目的は上記の問題点を解
消し、コストの増加を招くことなく、高い生産性で少量
多品種製品を製造することができる半導体装置の製造装
置及び半導体装置の製造方法を提供することにある。Therefore, an object of the present invention is to solve the above problems and to manufacture a semiconductor device manufacturing apparatus and a semiconductor device capable of manufacturing a small amount of a wide variety of products with high productivity without increasing the cost. To provide a method.
【００１４】[0014]
【課題を解決するための手段】本発明による半導体装置
の製造装置は、複数種類の半導体基板各々に共通する製
造工程を含む半導体装置の製造装置であって、遠紫外光
及び電子線各々に感光性を有する感光性有機材料被膜を
半導体基板に形成する手段と、前記遠紫外光で前記感光
性有機材料被膜に所定パターンを露光する手段と、前記
所定パターンが露光された前記感光性有機材料被膜に前
記電子線で他のパターンを露光する手段と、前記感光性
有機材料被膜が前記遠紫外光及び前記電子線各々で露光
された前記半導体基板を現像する手段とを備えている。A semiconductor device manufacturing apparatus according to the present invention is a semiconductor device manufacturing apparatus including a manufacturing process common to a plurality of types of semiconductor substrates, and is sensitive to far ultraviolet light and electron beams. For forming a photosensitive organic material coating having a property on a semiconductor substrate, a means for exposing a predetermined pattern on the photosensitive organic material coating with the far-ultraviolet light, and the photosensitive organic material coating on which the predetermined pattern is exposed. And means for exposing another pattern with the electron beam, and means for developing the semiconductor substrate exposed with the far-ultraviolet light and the electron beam.
【００１５】本発明による半導体装置の製造方法は、複
数種類の半導体基板各々に共通する製造工程を含む半導
体装置の製造方法であって、遠紫外光及び電子線各々に
感光性を有する感光性有機材料被膜を半導体基板に形成
する工程と、前記遠紫外光で前記感光性有機材料被膜に
所定パターンを露光する工程と、前記所定パターンが露
光された前記感光性有機材料被膜に前記電子線で他のパ
ターンを露光する工程と、前記感光性有機材料被膜が前
記遠紫外光及び前記電子線各々で露光された前記半導体
基板を現像する工程とを備えている。A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including a manufacturing process common to a plurality of types of semiconductor substrates, and is a photosensitive organic material having sensitivity to far ultraviolet light and electron beams. Forming a material film on a semiconductor substrate, exposing the photosensitive organic material film to a predetermined pattern with the far-ultraviolet light, and exposing the photosensitive organic material film having the predetermined pattern to the electron beam. And a step of developing the semiconductor substrate exposed with the far-ultraviolet light and the electron beam, respectively.
【００１６】[0016]
【作用】遠紫外光及び電子線各々に対して感光性を有す
るレジストを用い、マスクを介して遠紫外光で少量多品
種の回路パターンの共通部分を露光し、少量多品種の品
種毎に異なる部分を電子線で露光する。[Function] Using a resist sensitive to far-ultraviolet light and electron beam respectively, a common portion of a small amount of a wide variety of circuit patterns is exposed through a mask with a far-ultraviolet light. The part is exposed with an electron beam.
【００１７】これによって、少量多品種各々に最大限共
通する共通パターンを露光するための共通のマスクを用
いて遠紫外光による露光を行うことが可能となる。よっ
て、少量多品種製品を製造するために多数のレティクル
を必要とすることなく、露光装置で各ロット毎にレティ
クルを設置して露光可能状態とする必要もなくなるの
で、レティクル作成に要する時間及び費用を削減するこ
とが可能となる。This makes it possible to perform exposure with far-ultraviolet light by using a common mask for exposing a common pattern that is most common to each of a variety of small quantities. Therefore, it is not necessary to install a large number of reticles in order to manufacture small-quantity, high-mix type products, and it is not necessary to install reticles for each lot in the exposure apparatus to enable exposure. Can be reduced.
【００１８】また、半導体基板個々に対して電子線描画
装置で描画する範囲を最小限に抑えることができ、半導
体装置製造における生産性の改善を見込むことが可能と
なる。したがって、高い生産性で少量多品種製品を製造
することが可能となる。Further, it is possible to minimize the range of drawing on the individual semiconductor substrate by the electron beam drawing apparatus, and it is possible to expect the improvement in productivity in manufacturing the semiconductor device. Therefore, it becomes possible to manufacture a small amount of a wide variety of products with high productivity.
【００１９】[0019]
【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.
【００２０】図１は本発明の一実施例による半導体装置
の製造方法を示す工程図である。この図１を用いて本発
明の一実施例による半導体装置の製造工程について以下
説明する。FIG. 1 is a process chart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. A manufacturing process of a semiconductor device according to an embodiment of the present invention will be described below with reference to FIG.
【００２１】半導体基板（図示せず）に対するトランジ
スタの形成と配線層用のアルミニウム被膜の形成とから
なる成膜工程（図１の工程Ｓ１）が終了すると、その半
導体基板上に遠紫外光及び電子線各々に感光性を有する
レジスト、例えばポリビニルフェノール誘導体からなる
樹脂と光酸発生剤との混合物からなるポジ型化学増幅レ
ジスト［具体的には、ＳＩＰＬＥＹ社製の遠紫外光（２
５０ｎｍ程度）用ポジレジストＡＰＥＸ−Ｅ］を膜厚
１．５μｍとなるように塗布する（感光性有機材料塗
布）（図１の工程Ｓ２）。When the film forming step (step S1 in FIG. 1) consisting of forming a transistor on a semiconductor substrate (not shown) and forming an aluminum film for a wiring layer is completed, far-ultraviolet light and electrons are formed on the semiconductor substrate. A resist having photosensitivity to each line, for example, a positive type chemically amplified resist composed of a mixture of a resin composed of a polyvinylphenol derivative and a photo-acid generator [specifically, a far ultraviolet light (2)
Positive resist APEX-E] (approx. 50 nm) is applied to a film thickness of 1.5 μm (application of photosensitive organic material) (step S2 in FIG. 1).
【００２２】続いて、５０枚の半導体基板からなるロッ
トに、ＫｒＦエキシマレーザを露光光源とする露光装置
（図示せず）を用いて配線パターンを転写する（図１の
工程Ｓ３）。このとき、転写される配線パターンはロッ
トに含まれる複数品種に対して最大限共通する共通パタ
ーンであり、電子線描画による露光パターン数を最小限
に抑えられるようにしたものである。Subsequently, a wiring pattern is transferred to a lot of 50 semiconductor substrates by using an exposure device (not shown) having a KrF excimer laser as an exposure light source (step S3 in FIG. 1). At this time, the transferred wiring pattern is a common pattern that is common to a plurality of products included in the lot, and the number of exposure patterns by electron beam drawing can be minimized.
【００２３】この遠紫外光による露光の後に、複数品種
各々の独自パターンを露光する電子線描画１，電子線描
画２，電子線描画３を電子線描画装置（図示せず）で行
い（図１の工程Ｓ４）、それから半導体基板の現像工程
（図１の工程Ｓ５）及びエッチング工程（図１の工程Ｓ
６）を行う。After the exposure with the far-ultraviolet light, electron beam drawing 1, electron beam drawing 2, and electron beam drawing 3 for exposing unique patterns of each of a plurality of types are performed by an electron beam drawing device (not shown) (see FIG. 1). Step S4), then the semiconductor substrate developing step (step S5 in FIG. 1) and the etching step (step S in FIG. 1).
Perform 6).
【００２４】したがって、遠紫外光による露光では複数
品種各々に最大限共通する共通パターンを露光するため
の共通のマスクを用いることができるので、少量多品種
製品を製造するために多数のレティクルを必要とするこ
となく、露光装置で各ロット毎にレティクルを設置して
露光可能状態とする必要もなくなるので、レティクル作
成に要する時間及び費用を削減することができる。Therefore, since a common mask for exposing a common pattern that is most common to each of a plurality of products can be used in the exposure by far-ultraviolet light, a large number of reticles are required to manufacture a small amount of a large variety of products. Since it is not necessary to install a reticle for each lot in the exposure apparatus to bring it into an exposure-enabled state, it is possible to reduce the time and cost required to create the reticle.
【００２５】また、半導体基板個々に対して電子線描画
装置で描画する範囲を最小限に抑えることができる。よ
って、半導体装置製造における生産性の改善を見込むこ
とが可能となる。Further, it is possible to minimize the drawing range of each semiconductor substrate by the electron beam drawing apparatus. Therefore, it is possible to expect an improvement in productivity in manufacturing a semiconductor device.
【００２６】図２は本発明の一実施例による配線パター
ンの形成例を示す図である。図において、長い配線パタ
ーン４はロットに含まれる複数品種に対して最大限共通
する共通パターンで、遠紫外光で露光転写されるパター
ンを示している。FIG. 2 is a diagram showing an example of forming a wiring pattern according to an embodiment of the present invention. In the figure, a long wiring pattern 4 is a common pattern that is common to a plurality of products included in a lot at the maximum, and shows a pattern that is exposed and transferred by far ultraviolet light.
【００２７】領域１〜３各々は複数品種各々の独自パタ
ーンで、回路構成上接続してはいけないパターンであ
り、電子線により露光転写されるパターンを示してい
る。すなわち、遠紫外光で露光転写された長い配線パタ
ーン４において、回路上必要最小限な領域１〜３各々が
電子線により露光転写される。Each of the areas 1 to 3 is a unique pattern of each of a plurality of products, which is a pattern that should not be connected in terms of circuit configuration, and shows a pattern that is exposed and transferred by an electron beam. That is, in the long wiring pattern 4 exposed and transferred with far-ultraviolet light, the minimum necessary areas 1 to 3 on the circuit are exposed and transferred by the electron beam.
【００２８】図３は本発明の一実施例による電子線の露
光で用いられる位置合せ用のアライメントマークを示す
図である。図３（ａ）は十字形の位置合せ用のアライメ
ントマークを示す図であり、図３（ｂ）は井桁形の位置
合せ用のアライメントマークを示す図である。FIG. 3 is a view showing alignment marks for alignment used in electron beam exposure according to an embodiment of the present invention. 3A is a diagram showing a cross-shaped alignment mark for alignment, and FIG. 3B is a diagram showing a cross-shaped alignment mark for alignment.
【００２９】本発明の一実施例では遠紫外光による露光
と電子線による露光との位置合せ精度が高いことが必須
の要件となる。この要件を実現するために、該当リソグ
ラフィ工程よりも前のレティクルを用いた光露光工程
で、電子線による露光で用いる十字形のアライメントマ
ークＡまたは井桁形のアライメントマークＢを予め形成
しておく。In one embodiment of the present invention, it is an essential requirement that the alignment accuracy between the exposure with the far ultraviolet light and the exposure with the electron beam is high. In order to realize this requirement, the cross-shaped alignment mark A or the cross-shaped alignment mark B used in the exposure with the electron beam is previously formed in the light exposure process using the reticle prior to the corresponding lithography process.
【００３０】この種のアライメントマークＡ，Ｂを用い
た場合、電子線露光においては０．０５〜０．０７μｍ
の重ね合せ精度が得られており、０．３μｍ程度の配線
パターンを形成する上では何等支障はない。When the alignment marks A and B of this kind are used, the electron beam exposure is 0.05 to 0.07 μm.
Is obtained, and there is no problem in forming a wiring pattern of about 0.3 μm.
【００３１】図４は本発明の他の実施例による半導体装
置の製造方法を示す工程図である。この図４を用いて本
発明の他の実施例による半導体装置の製造工程について
以下説明する。FIG. 4 is a process chart showing a method of manufacturing a semiconductor device according to another embodiment of the present invention. A manufacturing process of a semiconductor device according to another embodiment of the present invention will be described below with reference to FIG.
【００３２】半導体基板に対するトランジスタの形成と
配線層用のアルミニウム被膜の形成とからなる成膜工程
（図４の工程Ｓ１１）が終了すると、その半導体基板上
に遠紫外光及び電子線各々に感光性を有するレジストを
塗布する（感光性有機材料塗布）（図４の工程Ｓ１
２）。When the film forming step (step S11 in FIG. 4) including the formation of the transistor on the semiconductor substrate and the formation of the aluminum film for the wiring layer is completed, the semiconductor substrate is exposed to far-ultraviolet light and electron beams, respectively. Coating of a resist having (a photosensitive organic material coating) (step S1 of FIG. 4)
2).
【００３３】続いて、５０枚の半導体基板からなるロッ
トに対して、複数品種各々の独自パターンを露光する電
子線描画１，電子線描画２，電子線描画３を電子線描画
装置で行う（図４の工程Ｓ１３）。Subsequently, an electron beam drawing apparatus 1, an electron beam drawing apparatus 2, and an electron beam drawing apparatus 3 for exposing unique patterns of a plurality of types of products are performed by an electron beam drawing apparatus on a lot of 50 semiconductor substrates (see FIG. 4 step S13).
【００３４】その後に、ＫｒＦエキシマレーザを露光光
源とする露光装置を用いて配線パターンを転写する（図
４の工程Ｓ１４）。このとき、転写される配線パターン
はロットに含まれる複数品種に対して最大限共通する共
通パターンであり、電子線描画による露光パターン数を
最小限に抑えられるようにしたものである。After that, the wiring pattern is transferred using an exposure device using a KrF excimer laser as an exposure light source (step S14 in FIG. 4). At this time, the transferred wiring pattern is a common pattern that is common to a plurality of products included in the lot, and the number of exposure patterns by electron beam drawing can be minimized.
【００３５】この遠紫外光による露光の後に、半導体基
板の現像工程（図４の工程Ｓ１５）及びエッチング工程
（図４の工程Ｓ１６）を行う。After the exposure with the far-ultraviolet light, a developing process (process S15 of FIG. 4) and an etching process (process S16 of FIG. 4) of the semiconductor substrate are performed.
【００３６】したがって、遠紫外光による露光では複数
品種各々に最大限共通する共通パターンを露光するため
の共通のマスクを用いることができるので、少量多品種
製品を製造するために多数のレティクルを必要とするこ
となく、露光装置で各ロット毎にレティクルを設置して
露光可能状態とする必要もなくなるので、レティクル作
成に要する時間及び費用を削減することができる。Therefore, since a common mask for exposing a common pattern that is most common to each of a plurality of products can be used in the exposure by far ultraviolet light, a large number of reticles are required to manufacture a small amount of a large variety of products. Since it is not necessary to install a reticle for each lot in the exposure apparatus to bring it into an exposure-enabled state, it is possible to reduce the time and cost required to create the reticle.
【００３７】また、半導体基板個々に対して電子線描画
装置で描画する範囲を最小限に抑えることができる。よ
って、半導体装置製造における生産性の改善を見込むこ
とが可能となる。Further, it is possible to minimize the drawing range of each semiconductor substrate by the electron beam drawing apparatus. Therefore, it is possible to expect an improvement in productivity in manufacturing a semiconductor device.
【００３８】この場合でも、アライメントに関しては上
述した処理と全く同様であり、前工程までに遠紫外光露
光及び電子線露光の両方のアライメントマークＡ，Ｂを
形成しておき、遠紫外光露光及び電子線露光各々のマー
クに対してアライメントを行う。Even in this case, the alignment is exactly the same as the above-mentioned processing, and the alignment marks A and B for both far-ultraviolet light exposure and electron beam exposure are formed by the previous step, and far-ultraviolet light exposure and Electron beam exposure Aligns each mark.
【００３９】図５は本発明の別の実施例による配線パタ
ーンの形成例を示す図である。図において、適当な長さ
で区切られた配線パターン５各々はロットに含まれる複
数品種に対して最大限共通する共通パターンで、遠紫外
光で露光転写されるパターンを示している。FIG. 5 is a diagram showing an example of forming a wiring pattern according to another embodiment of the present invention. In the figure, each of the wiring patterns 5 divided into appropriate lengths is a common pattern that is common to a plurality of products included in a lot and is a pattern that is exposed and transferred by far ultraviolet light.
【００４０】配線パターン５間を接続する配線パターン
６各々は複数品種各々の独自パターンで、電子線により
露光転写されるパターンを示している。すなわち、遠紫
外光で露光転写された配線パターン５に対して、それら
の間で接続が必要な箇所を接続するために配線パターン
６各々が電子線により露光転写される。Each of the wiring patterns 6 for connecting the wiring patterns 5 is a unique pattern of each of a plurality of types, and shows a pattern which is exposed and transferred by an electron beam. That is, each wiring pattern 6 is exposed and transferred by an electron beam to the wiring pattern 5 that is exposed and transferred with far-ultraviolet light so as to connect the portions that require connection between them.
【００４１】この場合、製造工程のフローは図１に示す
本発明の一実施例と同様であるが、成膜工程の後に工程
Ｓ２で半導体基板上に塗布するレジストとしてネガ型電
子線レジスト、例えばノボラック樹脂とメラミン誘導体
よりなる架橋剤と光酸発生剤との混合物からなるネガ型
化学増幅レジスト［具体的には、ＳＩＰＬＥＹ社製の化
学増幅型ネガレジストＳＡＬ ６０１］を用いている。In this case, the manufacturing process flow is the same as that of the embodiment of the present invention shown in FIG. 1, but a negative electron beam resist, for example, a negative electron beam resist, is applied as a resist applied on the semiconductor substrate in step S2 after the film forming process. A negative chemically amplified resist [specifically, a chemically amplified negative resist SAL 601 manufactured by SIPLEY] made of a mixture of a novolak resin, a crosslinking agent made of a melamine derivative, and a photoacid generator is used.
【００４２】このように、遠紫外光及び電子線各々に対
して感光性を有するレジストを用い、マスクを介して遠
紫外光で少量多品種の回路パターンの共通部分を露光
し、少量多品種の品種毎に異なる部分を電子線で露光す
ることによって、少量多品種各々に最大限共通する共通
パターンを露光するための共通のマスクを用いて遠紫外
光による露光を行うことができる。As described above, a common portion of a small amount of a variety of circuit patterns is exposed through the mask using a resist having a sensitivity to far ultraviolet light and an electron beam respectively, and is exposed through a mask. By exposing a different portion for each type with an electron beam, it is possible to perform exposure with far-ultraviolet light using a common mask for exposing a common pattern that is most common to each type of small quantity.
【００４３】よって、少量多品種製品を製造するために
多数のレティクルを必要とすることなく、露光装置で各
ロット毎にレティクルを設置して露光可能状態とする必
要もなくなるので、レティクル作成に要する時間及び費
用を削減することができる。Therefore, it is not necessary to provide a large number of reticles to manufacture a small amount of a wide variety of products, and it is not necessary to install reticles for each lot in the exposure apparatus to make the exposure possible. Time and cost can be saved.
【００４４】また、半導体基板個々に対して電子線描画
装置で描画する範囲を最小限に抑えることができるの
で、半導体装置製造における生産性の改善を見込むこと
が可能となる。したがって、高い生産性で少量多品種製
品を製造することができる。Further, since the range of drawing by the electron beam drawing apparatus on each semiconductor substrate can be minimized, it is possible to expect the improvement in productivity in manufacturing the semiconductor device. Therefore, it is possible to manufacture a small amount of a wide variety of products with high productivity.
【００４５】尚、請求項の記載に関連して本発明はさら
に次のような態様をとりうる。The present invention can have the following aspects in relation to the description of the claims.
【００４６】（１）複数種類の半導体基板各々に共通す
る製造工程を含む半導体装置の製造装置であって、遠紫
外光及び電子線各々に感光性を有する感光性有機材料被
膜を半導体基板に形成する手段と、前記遠紫外光で前記
感光性有機材料被膜に前記複数種類の半導体基板各々に
共通する所定パターンを露光する手段と、前記所定パタ
ーンが露光された前記感光性有機材料被膜に前記電子線
で前記複数種類の半導体基板各々に固有の独自パターン
を露光する手段と、前記感光性有機材料被膜が前記遠紫
外光及び前記電子線各々で露光された前記半導体基板を
現像する手段とを有することを特徴とする半導体装置の
製造装置。(1) A semiconductor device manufacturing apparatus including a manufacturing process common to a plurality of types of semiconductor substrates, wherein a photosensitive organic material film having photosensitivity to far ultraviolet light and electron beam is formed on the semiconductor substrate. Means for exposing the photosensitive organic material film with a predetermined pattern common to each of the plurality of types of semiconductor substrates with the far-ultraviolet light, and the electron on the photosensitive organic material film exposed with the predetermined pattern. And a means for exposing the semiconductor substrate exposed by the far-ultraviolet light and the electron beam to the photosensitive organic material film. A semiconductor device manufacturing apparatus characterized by the above.
【００４７】（２）前記遠紫外光は、略１９０ｎｍ乃至
３００ｎｍの遠紫外光であることを特徴とする（１）記
載の半導体装置の製造方法。(2) The method of manufacturing a semiconductor device according to (1), wherein the far-ultraviolet light is far-ultraviolet light having a wavelength of approximately 190 nm to 300 nm.
【００４８】（３）複数種類の半導体基板各々に共通す
る製造工程を含む半導体装置の製造装置であって、略１
９０ｎｍ乃至３００ｎｍの遠紫外光及び電子線各々に感
光性を有する感光性有機材料被膜を半導体基板に形成す
る手段と、前記遠紫外光で前記感光性有機材料被膜に所
定パターンを露光する手段と、前記所定パターンが露光
された前記感光性有機材料被膜に前記電子線で他のパタ
ーンを露光する手段と、前記感光性有機材料被膜が前記
遠紫外光及び前記電子線各々で露光された前記半導体基
板を現像する手段とを有することを特徴とする半導体装
置の製造装置。(3) A semiconductor device manufacturing apparatus including a manufacturing process common to each of a plurality of types of semiconductor substrates, which is approximately 1
Means for forming, on a semiconductor substrate, a photosensitive organic material coating having a sensitivity to far-ultraviolet light of 90 nm to 300 nm and an electron beam, and means for exposing the photosensitive organic material coating to a predetermined pattern with the far-ultraviolet light, Means for exposing the photosensitive organic material film on which the predetermined pattern has been exposed to another pattern by the electron beam, and the semiconductor substrate on which the photosensitive organic material film has been exposed by the far-ultraviolet light and the electron beam, respectively. And a means for developing the semiconductor device.
【００４９】（４）前記半導体基板は、前記遠紫外光に
よる露光及び前記電子線による露光に用いられる位置合
せ用のアライメントマークを含むことを特徴とする
（１）から（３）のいずれか記載の半導体装置の製造方
法。(4) The semiconductor substrate includes alignment marks for alignment used for exposure with the far-ultraviolet light and exposure with the electron beam. (1) to (3) Of manufacturing a semiconductor device of.
【００５０】（５）複数種類の半導体基板各々に共通す
る製造工程を含む半導体装置の製造装置であって、遠紫
外光及び電子線各々に感光性を有する感光性有機材料被
膜を半導体基板に形成する手段と、前記遠紫外光で前記
感光性有機材料被膜に所定パターンを露光する手段と、
前記所定パターンが露光された前記感光性有機材料被膜
に前記電子線で他のパターンを露光する手段と、前記感
光性有機材料被膜が前記遠紫外光及び前記電子線各々で
露光された前記半導体基板を現像する手段と、前記遠紫
外光による露光及び前記電子線による露光に用いられる
位置合せ用のアライメントマークとを有することを特徴
とする半導体装置の製造装置。(5) A semiconductor device manufacturing apparatus including a manufacturing process common to a plurality of types of semiconductor substrates, wherein a photosensitive organic material film having photosensitivity to far ultraviolet light and electron beam is formed on the semiconductor substrate. And a means for exposing the photosensitive organic material film to a predetermined pattern with the far-ultraviolet light,
Means for exposing the photosensitive organic material film on which the predetermined pattern has been exposed to another pattern by the electron beam, and the semiconductor substrate on which the photosensitive organic material film has been exposed by the far-ultraviolet light and the electron beam, respectively. And an alignment mark for alignment used for the exposure with the far-ultraviolet light and the exposure with the electron beam.
【００５１】（６）前記他のパターンは、前記所定パタ
ーンのうち前記複数種類の半導体基板固有に回路構成上
接続してはいけないパターンであることを特徴とする
（１）から（５）のいずれか記載の半導体装置の製造装
置。(6) Any one of (1) to (5), wherein the other pattern is a pattern which is unique to the plurality of types of semiconductor substrates among the predetermined patterns and should not be connected in terms of circuit configuration. Or a semiconductor device manufacturing apparatus as described above.
【００５２】（７）複数種類の半導体基板各々に共通す
る製造工程を含む半導体装置の製造装置であって、遠紫
外光及び電子線各々に感光性を有する感光性有機材料被
膜を半導体基板に形成する手段と、前記遠紫外光で前記
感光性有機材料被膜に所定パターンを露光する手段と、
前記所定パターンが露光された前記感光性有機材料被膜
に前記電子線で前記所定パターンのうち前記複数種類の
半導体基板固有に回路構成上接続してはいけない他のパ
ターンを露光する手段と、前記感光性有機材料被膜が前
記遠紫外光及び前記電子線各々で露光された前記半導体
基板を現像する手段とを有することを特徴とする半導体
装置の製造装置。(7) A semiconductor device manufacturing apparatus including a manufacturing process common to a plurality of types of semiconductor substrates, in which a photosensitive organic material film having photosensitivity to far ultraviolet light and electron beam is formed on the semiconductor substrate. And a means for exposing the photosensitive organic material film to a predetermined pattern with the far-ultraviolet light,
The photosensitive organic material film on which the predetermined pattern has been exposed is exposed by the electron beam to another pattern of the predetermined pattern that should not be connected in the circuit configuration peculiar to the semiconductor substrates of the plurality of types; And a means for developing the semiconductor substrate exposed to the far-ultraviolet light and the electron beam, respectively.
【００５３】（８）前記他のパターンは、前記所定パタ
ーンを前記複数種類の半導体基板固有に回路構成上接続
するパターンであることを特徴とする（１）から（５）
のいずれか記載の半導体装置の製造装置。(8) The other pattern is a pattern that connects the predetermined pattern to the plurality of types of semiconductor substrates uniquely in terms of circuit configuration (1) to (5).
An apparatus for manufacturing a semiconductor device according to any one of 1.
【００５４】（９）複数種類の半導体基板各々に共通す
る製造工程を含む半導体装置の製造装置であって、遠紫
外光及び電子線各々に感光性を有する感光性有機材料被
膜を半導体基板に形成する手段と、前記遠紫外光で前記
感光性有機材料被膜に所定パターンを露光する手段と、
前記所定パターンが露光された前記感光性有機材料被膜
に前記電子線で前記所定パターンを前記複数種類の半導
体基板固有に回路構成上接続する他のパターンを露光す
る手段と、前記感光性有機材料被膜が前記遠紫外光及び
前記電子線各々で露光された前記半導体基板を現像する
手段とを有することを特徴とする半導体装置の製造装
置。(9) A semiconductor device manufacturing apparatus including a manufacturing process common to a plurality of types of semiconductor substrates, wherein a photosensitive organic material film having photosensitivity to far-ultraviolet light and electron beam is formed on the semiconductor substrate. And a means for exposing the photosensitive organic material film to a predetermined pattern with the far-ultraviolet light,
Means for exposing the photosensitive organic material coating film on which the predetermined pattern has been exposed to another pattern that connects the predetermined pattern with the electron beam in a circuit configuration unique to the plurality of types of semiconductor substrates, and the photosensitive organic material coating film. And a means for developing the semiconductor substrate exposed to the far-ultraviolet light and the electron beam, respectively.
【００５５】[0055]
【発明の効果】以上説明したように本発明によれば、遠
紫外光及び電子線各々に対して感光性を有するレジスト
を用い、マスクを介して遠紫外光で少量多品種の回路パ
ターンの共通部分を露光し、少量多品種の品種毎に異な
る部分を電子線で露光することによって、コストの増加
を招くことなく、高い生産性で少量多品種製品を製造す
ることができるという効果がある。As described above, according to the present invention, a resist having photosensitivity to far-ultraviolet light and electron beam is used, and a small amount of a wide variety of circuit patterns can be shared by far-ultraviolet light through a mask. By exposing a portion and exposing a different portion for each kind of a small amount of a wide variety of products with an electron beam, there is an effect that a small amount of a large variety of products can be manufactured with high productivity without causing an increase in cost.
【図１】本発明の一実施例による半導体装置の製造方法
を示す工程図である。FIG. 1 is a process chart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施例による配線パターンの形成例
を示す図である。FIG. 2 is a diagram showing an example of forming a wiring pattern according to an embodiment of the present invention.
【図３】（ａ）は十字形の位置合せ用のアライメントマ
ークを示す図、（ｂ）は井桁形の位置合せ用のアライメ
ントマークを示す図である。3A is a diagram showing a cross-shaped alignment mark for alignment, and FIG. 3B is a diagram showing a cross-beam alignment mark for alignment.
【図４】本発明の他の実施例による半導体装置の製造方
法を示す工程図である。FIG. 4 is a process drawing showing a method of manufacturing a semiconductor device according to another embodiment of the present invention.
【図５】本発明の別の実施例による配線パターンの形成
例を示す図である。FIG. 5 is a diagram showing an example of forming a wiring pattern according to another embodiment of the present invention.
【図６】従来例による半導体装置の製造方法を示す工程
図である。FIG. 6 is a process chart showing a method of manufacturing a semiconductor device according to a conventional example.
１〜３ 領域 ４ 配線パターン ５ 電子描画パターン 1-3 regions 4 wiring patterns 5 electronic drawing patterns
Claims (7)
造工程を含む半導体装置の製造装置であって、遠紫外光
及び電子線各々に感光性を有する感光性有機材料被膜を
前記半導体基板に形成する手段と、前記遠紫外光で前記
感光性有機材料被膜に所定パターンを露光する手段と、
前記所定パターンが露光された前記感光性有機材料被膜
に前記電子線で他のパターンを露光する手段と、前記感
光性有機材料被膜が前記遠紫外光及び前記電子線各々で
露光された前記半導体基板を現像する手段とを有するこ
とを特徴とする半導体装置の製造装置。1. A semiconductor device manufacturing apparatus including a manufacturing process common to a plurality of types of semiconductor substrates, wherein a photosensitive organic material film having photosensitivity to far ultraviolet light and electron beam is formed on the semiconductor substrate. And a means for exposing the photosensitive organic material film to a predetermined pattern with the far-ultraviolet light,
Means for exposing the photosensitive organic material film on which the predetermined pattern has been exposed to another pattern by the electron beam, and the semiconductor substrate on which the photosensitive organic material film has been exposed by the far-ultraviolet light and the electron beam, respectively. And a means for developing the semiconductor device.
造工程を含む半導体装置の製造方法であって、遠紫外光
及び電子線各々に感光性を有する感光性有機材料被膜を
前記半導体基板に形成する工程と、前記遠紫外光で前記
感光性有機材料被膜に所定パターンを露光する工程と、
前記所定パターンが露光された前記感光性有機材料被膜
に前記電子線で他のパターンを露光する工程と、前記感
光性有機材料被膜が前記遠紫外光及び前記電子線各々で
露光された前記半導体基板を現像する工程とを有するこ
とを特徴とする半導体装置の製造方法。2. A method of manufacturing a semiconductor device including a manufacturing process common to a plurality of types of semiconductor substrates, wherein a photosensitive organic material film having photosensitivity to far ultraviolet light and electron beam is formed on the semiconductor substrate. And a step of exposing a predetermined pattern to the photosensitive organic material film with the far-ultraviolet light,
A step of exposing another pattern with the electron beam to the photosensitive organic material film on which the predetermined pattern has been exposed; and the semiconductor substrate on which the photosensitive organic material film has been exposed with the far-ultraviolet light and the electron beam, respectively. And a step of developing the semiconductor device.
導体基板各々に共通する共通パターンであり、 前記他のパターンは、前記複数種類の半導体基板各々に
固有の独自パターンであることを特徴とする請求項２記
載の半導体装置の製造方法。3. The predetermined pattern is a common pattern common to each of the plurality of types of semiconductor substrates, and the other pattern is a unique pattern unique to each of the plurality of types of semiconductor substrates. The method for manufacturing a semiconductor device according to claim 2.
０ｎｍの遠紫外光であることを特徴とする請求項２また
は請求項３記載の半導体装置の製造方法。4. The far-ultraviolet light is approximately 190 nm to 30 nm.
4. The method for manufacturing a semiconductor device according to claim 2, wherein the far ultraviolet light is 0 nm.
露光及び前記電子線による露光に用いられる位置合せ用
のアライメントマークを含むことを特徴とする請求項２
から請求項４のいずれか記載の半導体装置の製造方法。5. The semiconductor substrate includes alignment marks for alignment used for exposure with the far-ultraviolet light and exposure with the electron beam.
6. The method for manufacturing a semiconductor device according to claim 4.
のうち前記複数種類の半導体基板固有に回路構成上接続
してはいけないパターンであることを特徴とする請求項
２から請求項５のいずれか記載の半導体装置の製造方
法。6. The pattern according to claim 2, wherein the other pattern is a pattern that must not be connected to the plurality of types of semiconductor substrates uniquely in the circuit configuration among the predetermined patterns. A method for manufacturing a semiconductor device as described above.
を前記複数種類の半導体基板固有に回路構成上接続する
パターンであることを特徴とする請求項２から請求項５
のいずれか記載の半導体装置の製造方法。7. The second pattern according to claim 2, wherein the other pattern is a pattern that connects the predetermined pattern unique to the plurality of types of semiconductor substrates in terms of circuit configuration.
9. A method of manufacturing a semiconductor device according to any one of 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7153734A JPH097924A (en) | 1995-06-21 | 1995-06-21 | Equipment and method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7153734A JPH097924A (en) | 1995-06-21 | 1995-06-21 | Equipment and method for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH097924A true JPH097924A (en) | 1997-01-10 |
Family
ID=15568938
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7153734A Pending JPH097924A (en) | 1995-06-21 | 1995-06-21 | Equipment and method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH097924A (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10189415A (en) * | 1996-12-26 | 1998-07-21 | Hitachi Ltd | Method and device for forming resist pattern |
| JPH11162844A (en) * | 1997-09-25 | 1999-06-18 | Toshiba Corp | Pattern formation |
| US5989759A (en) * | 1997-02-28 | 1999-11-23 | Kabushiki Kaisha Toshiba | Pattern forming method using alignment from latent image or base pattern on substrate |
| US5994030A (en) * | 1997-02-28 | 1999-11-30 | Kabushiki Kaisha Toshiba | Pattern-forming method and lithographic system |
| US6337163B1 (en) | 1998-09-22 | 2002-01-08 | Kabushiki Kaisha Toshiba | Method of forming a pattern by making use of hybrid exposure |
| WO2006120896A1 (en) * | 2005-05-02 | 2006-11-16 | Tokyo Ohka Kogyo Co., Ltd. | Positive resist composition and method for forming resist pattern |
| WO2006120845A1 (en) * | 2005-05-11 | 2006-11-16 | Tokyo Ohka Kogyo Co., Ltd. | Negative resist composition and method for forming resist pattern |
| JP2006317584A (en) * | 2005-05-11 | 2006-11-24 | Tokyo Ohka Kogyo Co Ltd | NEGATIVE RESIST COMPOSITION USED IN PROCESS WHERE EXPOSURE IS PERFORMED USING AT LEAST TWO KINDS OF EXPOSURE LIGHT SOURCES SELECTED FROM G-LINE, I-LINE, KrF EXCIMER LASER, AND ELECTRON BEAM, AND RESIST PATTERN FORMING METHOD |
| WO2018047981A1 (en) * | 2016-09-08 | 2018-03-15 | Mapper Lithography Ip B.V. | Secure chips with serial numbers |
| JP2018041950A (en) * | 2016-09-08 | 2018-03-15 | マッパー・リソグラフィー・アイピー・ビー．ブイ． | Method and system for fabricating unique chip using charged particle multi-beamlet lithography system |
| WO2018047985A1 (en) * | 2016-09-08 | 2018-03-15 | Mapper Lithography Ip B.V. | Fabricating unique chips using a charged particle multi-beamlet lithography system |
| JP2018074133A (en) * | 2016-10-27 | 2018-05-10 | マッパー・リソグラフィー・アイピー・ビー．ブイ． | Manufacture of unique chip by using charged particle multi-beamlet lithography system |
| JPWO2018061945A1 (en) * | 2016-09-30 | 2019-07-11 | 株式会社ニコン | Measurement system, substrate processing system, and device manufacturing method |
| JP2019522820A (en) * | 2016-07-19 | 2019-08-15 | エーエスエムエル ネザーランズ ビー．ブイ． | Determining the combination of patterns to be applied to a substrate in a lithography step |
| US10522472B2 (en) | 2016-09-08 | 2019-12-31 | Asml Netherlands B.V. | Secure chips with serial numbers |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63278230A (en) * | 1987-05-09 | 1988-11-15 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH05343278A (en) * | 1992-06-10 | 1993-12-24 | Nec Corp | Manufacture of semiconductor device |
-
1995
- 1995-06-21 JP JP7153734A patent/JPH097924A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63278230A (en) * | 1987-05-09 | 1988-11-15 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH05343278A (en) * | 1992-06-10 | 1993-12-24 | Nec Corp | Manufacture of semiconductor device |
Cited By (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10189415A (en) * | 1996-12-26 | 1998-07-21 | Hitachi Ltd | Method and device for forming resist pattern |
| US6941008B2 (en) | 1997-02-28 | 2005-09-06 | Kabushiki Kaisha Toshiba | Pattern forming method |
| US5989759A (en) * | 1997-02-28 | 1999-11-23 | Kabushiki Kaisha Toshiba | Pattern forming method using alignment from latent image or base pattern on substrate |
| US5994030A (en) * | 1997-02-28 | 1999-11-30 | Kabushiki Kaisha Toshiba | Pattern-forming method and lithographic system |
| US6093931A (en) * | 1997-02-28 | 2000-07-25 | Kabushiki Kaisha Toshiba | Pattern-forming method and lithographic system |
| US6147355A (en) * | 1997-02-28 | 2000-11-14 | Kabushiki Kaisha Toshiba | Pattern forming method |
| JPH11162844A (en) * | 1997-09-25 | 1999-06-18 | Toshiba Corp | Pattern formation |
| US6337163B1 (en) | 1998-09-22 | 2002-01-08 | Kabushiki Kaisha Toshiba | Method of forming a pattern by making use of hybrid exposure |
| WO2006120896A1 (en) * | 2005-05-02 | 2006-11-16 | Tokyo Ohka Kogyo Co., Ltd. | Positive resist composition and method for forming resist pattern |
| US7816072B2 (en) | 2005-05-02 | 2010-10-19 | Tokyo Ohka Kogyo Co., Ltd. | Positive resist composition and method for forming resist pattern |
| WO2006120845A1 (en) * | 2005-05-11 | 2006-11-16 | Tokyo Ohka Kogyo Co., Ltd. | Negative resist composition and method for forming resist pattern |
| JP2006317584A (en) * | 2005-05-11 | 2006-11-24 | Tokyo Ohka Kogyo Co Ltd | NEGATIVE RESIST COMPOSITION USED IN PROCESS WHERE EXPOSURE IS PERFORMED USING AT LEAST TWO KINDS OF EXPOSURE LIGHT SOURCES SELECTED FROM G-LINE, I-LINE, KrF EXCIMER LASER, AND ELECTRON BEAM, AND RESIST PATTERN FORMING METHOD |
| US11747738B2 (en) | 2016-07-19 | 2023-09-05 | Asml Netherlands B.V. | Determining the combination of patterns to be applied to a substrate in a lithography step |
| JP2019522820A (en) * | 2016-07-19 | 2019-08-15 | エーエスエムエル ネザーランズ ビー．ブイ． | Determining the combination of patterns to be applied to a substrate in a lithography step |
| WO2018047985A1 (en) * | 2016-09-08 | 2018-03-15 | Mapper Lithography Ip B.V. | Fabricating unique chips using a charged particle multi-beamlet lithography system |
| US10714427B2 (en) | 2016-09-08 | 2020-07-14 | Asml Netherlands B.V. | Secure chips with serial numbers |
| WO2018047981A1 (en) * | 2016-09-08 | 2018-03-15 | Mapper Lithography Ip B.V. | Secure chips with serial numbers |
| US11688694B2 (en) | 2016-09-08 | 2023-06-27 | Asml Netherlands B.V. | Secure chips with serial numbers |
| JP2018041950A (en) * | 2016-09-08 | 2018-03-15 | マッパー・リソグラフィー・アイピー・ビー．ブイ． | Method and system for fabricating unique chip using charged particle multi-beamlet lithography system |
| US11004800B2 (en) | 2016-09-08 | 2021-05-11 | Asml Netherlands B.V. | Secure chips with serial numbers |
| US10522472B2 (en) | 2016-09-08 | 2019-12-31 | Asml Netherlands B.V. | Secure chips with serial numbers |
| US11107718B2 (en) | 2016-09-30 | 2021-08-31 | Nikon Corporation | Measurement system, substrate processing system, and device manufacturing method |
| US11430684B2 (en) | 2016-09-30 | 2022-08-30 | Nikon Corporation | Measurement system, substrate processing system, and device manufacturing method |
| JPWO2018061945A1 (en) * | 2016-09-30 | 2019-07-11 | 株式会社ニコン | Measurement system, substrate processing system, and device manufacturing method |
| US11915961B2 (en) | 2016-09-30 | 2024-02-27 | Nikon Corporation | Measurement system, substrate processing system, and device manufacturing method |
| US10600733B2 (en) | 2016-10-27 | 2020-03-24 | Asml Netherlands B.V. | Fabricating unique chips using a charged particle multi-beamlet lithography system |
| US10418324B2 (en) | 2016-10-27 | 2019-09-17 | Asml Netherlands B.V. | Fabricating unique chips using a charged particle multi-beamlet lithography system |
| JP2018074133A (en) * | 2016-10-27 | 2018-05-10 | マッパー・リソグラフィー・アイピー・ビー．ブイ． | Manufacture of unique chip by using charged particle multi-beamlet lithography system |
| US11152302B2 (en) | 2016-10-27 | 2021-10-19 | Asml Netherlands B.V. | Fabricating unique chips using a charged particle multi-beamlet lithography system |
| US10079206B2 (en) | 2016-10-27 | 2018-09-18 | Mapper Lithography Ip B.V. | Fabricating unique chips using a charged particle multi-beamlet lithography system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6458606B2 (en) | Etch bias distribution across semiconductor wafer | |
| JPH097924A (en) | Equipment and method for manufacturing semiconductor device | |
| US20030054642A1 (en) | Production method of semiconductor device and production system of semiconductor device | |
| JPH05289307A (en) | Reticle and its production | |
| US6420077B1 (en) | Contact hole model-based optical proximity correction method | |
| US6656646B2 (en) | Fabrication method of semiconductor integrated circuit device | |
| JP2002196470A (en) | Method of manufacturing photomask and method of manufacturing semiconductor integrated circuit device | |
| US7795601B2 (en) | Method and apparatus to improve lithography throughput | |
| US7491648B2 (en) | Method of patterning a photoresist film using a lithographic | |
| CN1833205B (en) | Measuring the effect of flare on line width | |
| JPH09218500A (en) | Manufacture of resist patterns | |
| US20070015088A1 (en) | Method for lithographically printing tightly nested and isolated hole features using double exposure | |
| KR20090040614A (en) | Method for fabricating halftone phase shift mask | |
| JPH0448715A (en) | Manufacture of semiconductor device | |
| US6645707B2 (en) | Device manufacturing method | |
| JP2821394B2 (en) | Method for manufacturing semiconductor device | |
| KR100604041B1 (en) | Method for fabricating mask | |
| CN115793413B (en) | Super-resolution pattern implementation method and device based on alignment difference and double lithography | |
| JPH0544169B2 (en) | ||
| JP2595886B2 (en) | Method for manufacturing semiconductor device | |
| US6225134B1 (en) | Method of controlling linewidth in photolithography suitable for use in fabricating integrated circuits | |
| JPS63275115A (en) | Pattern forming method for semiconductor device | |
| JP3529967B2 (en) | Manufacturing method of photomask blanks with alignment marks | |
| KR100272519B1 (en) | Patterning method of semiconductor device | |
| KR20010028305A (en) | Method for revising registration |