JPS63275115A - Pattern forming method for semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the relative arrangement of patterns with excellent accuracy, by performing a developing process after a first exposure, and performing a second and the following exposures applying the position alignment mark contained in a pattern actually shown in a photoresist as a reference. CONSTITUTION:When a pattern A is exposed in order and subjected to a first development, the pattern A of a resist is formed in a region of the pattern A. In the case where positive resist of novolac system and the like is used, the resist is left as it is on the region of a pattern B because it is not exposed. When the pattern B is exposed in order by using a position alignment mark C in the pattern A, and a second development is performed, the pattern B wherein the relative position alignment to the pattern A is exactly finished can be obtained. Thereby, the relative arrangement of patterns formed by a plurality of exposure regions can be obtained with high accuracy.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a pattern forming method for semiconductor devices.

[Conventional technology]

Conventionally, pattern formation for this type of semiconductor device has been carried out by using a reduction projection exposure apparatus, exposing a pattern of one chip or a plurality of chip areas as one exposure area, sequentially exposing these exposure areas, and repeating movement. This has been done by forming a desired pattern over the entire surface of a semiconductor substrate.

[Problem that the invention seeks to solve]

With the miniaturization of semiconductor devices in reduction projection systems, if the diagonal projection lenses N and A are made larger to improve resolution, the exposure area must be made smaller. As the size tends to increase, it has become difficult to fit one chip area into one exposure area. Therefore, it has become necessary to divide one chip area into a plurality of exposure areas and transfer each one separately.

In such a case, the above-mentioned conventional method cannot particularly perform relative positioning between the exposed areas. Therefore, the positioning accuracy between the four exposure areas is determined by the positioning accuracy of the stage control system and the positioning accuracy of the reticle when forming the first layer pattern.

That is, as shown in FIG. 3, in the conventional method, after exposing pattern A, the reticle is replaced and pattern B is exposed to complete the exposure of one chip area. In this case, by replacing the reticle, the error component of reticle alignment can be corrected.
There is an error component due to the positioning accuracy of the stage control system, and this error component is much larger than the normal optical alignment accuracy of the glabella. Therefore, when one chip area is divided into multiple exposure areas as described above,
There was a drawback that a desired continuous pattern could not be obtained on the boundary line of the exposure area.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pattern forming method for a semiconductor device that can realize the relative arrangement of patterns formed by a plurality of exposure regions with high accuracy.

[Means for solving problems]

A semiconductor device pattern forming method of the present invention is a semiconductor device pattern forming method in which a circuit pattern is formed by exposing one chip forming area on a semiconductor wafer multiple times using a reduction projection exposure apparatus. After exposure, a development process is performed to make a pattern visible on the photoresist, and second and subsequent exposures are performed using alignment marks included in this made-up pattern as a reference.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a chip area on a semiconductor wafer for explaining a first embodiment of the present invention. In the first embodiment, a case will be described in which a reduction projection exposure apparatus is used that performs alignment using a light beam of a wavelength to which the resist is not sensitive.

In FIG. 1, one chip area is divided into two exposure areas, each of which is patterned using a different reticle. First, pattern A is sequentially exposed to perform the first phenomenon. As a result, a resist pattern A is formed in the pattern A region. If a positive resist such as a novolac resin type resist is used here, an unexposed diagonal resist remains in the area of pattern B. Next, pattern B is sequentially exposed using alignment marks C in pattern A, and a second development is performed to form pattern B, which is positioned with high precision relative to pattern A.

According to the first embodiment, since the patterns A and B formed in one chip area are positioned with relatively high precision, a desired continuous pattern can be obtained even on the boundary line of the exposure area. It will be done.

FIG. 2 is a plan view of a chip area on a semiconductor wafer for explaining a second embodiment of the present invention. In this second embodiment, alignment is performed using a light beam of a wavelength to which the resist is exposed, or a reduction projection exposure apparatus that performs alignment using a TTL method is used.

In FIG. 2, after forming pattern A, aligning pattern B with pattern A and performing the exposure phenomenon is the same as in the first embodiment, but light with a wavelength to which the resist is sensitive is used as alignment light. In some cases, in order to prevent the pattern A of the resist from being exposed to alignment light, it is necessary to provide a small blind or to place an alignment mark near the boundary line of the exposure area.

In addition, in the case of the TTL method, since it is necessary to overlap the alignment mark and the mark to be aligned, it is also necessary to set the alignment mark near the boundary line and provide an area where pattern A and pattern B overlap.

By paying attention to the position of the alignment mark in this manner, the present invention can be applied to a reduction projection exposure apparatus that uses alignment light to which the resist is exposed or performs TTL type alignment.

〔Effect of the invention〕

As explained above, in the present invention, when a circuit pattern is formed by exposing one chip forming area multiple times, a development process is performed after the first exposure to make the pattern visible on the photoresist. By performing the second and subsequent exposures with reference to the alignment marks included in the pattern, there is an effect that the relative arrangement of the patterns formed by the plurality of exposure areas can be realized with high precision.

[Brief explanation of drawings]

1 and 2 are plan views of chips and regions on a semiconductor wafer for explaining the first and second embodiments of the present invention, and FIG. 3 is a plan view of a conventional pattern forming method for a semiconductor device. FIG. A, B...pattern, C...alignment mark, D.
...A region where pattern A and pattern B overlap.

Claims (1)

[Claims] In a pattern forming method for a semiconductor device in which a circuit pattern is formed by exposing one chip forming area on a semiconductor wafer multiple times using a reduction projection exposure apparatus, a development process is performed after the first exposure to reveal a pattern on the photoresist. 1. A method for forming a pattern for a semiconductor device, comprising: exposing the pattern to light for a second time and thereafter using the alignment mark included in the exposed pattern as a reference.