JPS6233580B2 - - Google Patents

Info

Publication number
JPS6233580B2
JPS6233580B2 JP18723580A JP18723580A JPS6233580B2 JP S6233580 B2 JPS6233580 B2 JP S6233580B2 JP 18723580 A JP18723580 A JP 18723580A JP 18723580 A JP18723580 A JP 18723580A JP S6233580 B2 JPS6233580 B2 JP S6233580B2
Authority
JP
Japan
Prior art keywords
pattern
mask
substrate
pitch
exposure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP18723580A
Other languages
Japanese (ja)
Other versions
JPS57112753A (en
Inventor
Niwaji Majima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18723580A priority Critical patent/JPS57112753A/en
Priority to DE8181306134T priority patent/DE3173277D1/en
Priority to EP81306134A priority patent/EP0055620B1/en
Priority to US06/333,814 priority patent/US4408875A/en
Publication of JPS57112753A publication Critical patent/JPS57112753A/en
Publication of JPS6233580B2 publication Critical patent/JPS6233580B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70475Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20Exposure; Apparatus therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0286Programmable, customizable or modifiable circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0073Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
    • H05K3/0082Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces characterised by the exposure method of radiation-sensitive masks

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Description

【発明の詳細な説明】 本発明は露光機を用いて基板上にレジストパタ
ーンの形成を行う際の露光方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an exposure method for forming a resist pattern on a substrate using an exposure machine.

本発明は一般に用いられている紫外線露光機に
止まらず、X線および電子線露光機など基板と露
光光源との相対位置を移動することにより、レジ
ストパターンを複数個基板上に繰返し露光形成す
る方式に適用される。
The present invention is not limited to commonly used ultraviolet exposure machines, but also uses X-ray and electron beam exposure machines, etc., to repeatedly form resist patterns on a plurality of substrates by moving the relative position of the substrate and the exposure light source. applied to.

こゝで本露光方法が使用可能な被露光基板とし
ては、バブルメモリチツプ、半導体ICチツプ、
薄膜磁気ヘツド等の薄膜形成基板の他に、これら
基板を得る際のパターン形成用マスクをリピータ
を用いて作成する場合にも適用できる。
The substrates to be exposed to which this exposure method can be used include bubble memory chips, semiconductor IC chips,
In addition to thin film forming substrates such as thin film magnetic heads, the present invention can also be applied to the case where a repeater is used to create a pattern forming mask for obtaining these substrates.

本発明は1つのパターンが少なくとも2度の露
光により形成されているような場合に適用され、
基板或は露光光源の移動距離を変えることにより
マスクパターンと異なるレジストパターンを基板
上に形成するもので、こゝではバブルメモリチツ
プの導電パターンの接続および切断についての実
施例を基に本発明を説明する。
The present invention is applied to cases where one pattern is formed by at least two exposures,
A resist pattern different from a mask pattern is formed on a substrate by changing the moving distance of the substrate or the exposure light source.Here, the present invention will be described based on an example of connecting and cutting conductive patterns of a bubble memory chip. explain.

バブルメモリチツプは製作技術および材料の進
歩に従つて1チツプ内に収容されている磁気バル
ブの記憶容量は年とともに増加し、一方記憶媒体
である磁気バルブ径は減少し、これとともにAu
やNi−Cu等からなる導電パターンおよびパーマ
ロイ等からなる転送パターンは微少化している。
As bubble memory chips progress in manufacturing technology and materials, the storage capacity of the magnetic valves housed in one chip increases over the years, while the diameter of the magnetic valves that serve as storage media decreases.
Conductive patterns made of materials such as or Ni-Cu and transfer patterns made of permalloy are becoming smaller.

例えば2μmのバルブ径を用いた記憶容量1M
ビツトのチツプの場合の最少パターン寸法は約1
μmとなり、従来技術のコンタクト露光方式では
無理であるため通常1/10縮小型の投影露光機が用
いられている。
For example, storage capacity 1M using a valve diameter of 2μm
The minimum pattern size for bit chips is approximately 1
μm, which is impossible with conventional contact exposure methods, so a 1/10 reduction type projection exposure machine is usually used.

こゝで1Mビツトのチツプの寸法は10mm角とな
り、現在最も高性能である投影露光機を用いても
10mm角の全領域に互つて1μmのパターンを形成
するのは歩留りの点から難しい。そこで投影露光
機の分解能の悪い4隅を使用せず、比較的分解能
の良い中心部を用い、500Kビツトのマスクパタ
ーンを2回隣接して露光し、1Mビツトのパター
ンとする方式がとられている。
The size of a 1M-bit chip is now 10 mm square, and even with today's most high-performance projection exposure machine,
It is difficult to form 1 μm patterns over the entire 10 mm square area from the viewpoint of yield. Therefore, a method was adopted in which a 500K-bit mask pattern was exposed twice adjacently to form a 1M-bit pattern by using the center part, which had relatively good resolution, instead of using the four corners of the projection exposure machine, which had poor resolution. There is.

このようなパターン形成においては転送パター
ンのように相互に独立したパターンの場合は差支
えないが、ゲート回路またはセンス回路のように
双方のパターンの導電部分を接続する必要がある
導電パターンの場合、従来は完成後のチツプを磁
器基板に装着後、磁器基板上に印刷配線されてい
る導体パターンを用いてワイヤーボンデイング
し、これにより2つの導体パターンの接続が行わ
れていた。
In such pattern formation, there is no problem in the case of mutually independent patterns such as transfer patterns, but in the case of conductive patterns that need to connect the conductive parts of both patterns such as gate circuits or sense circuits, conventional After the completed chip was mounted on a ceramic substrate, wire bonding was performed using a conductor pattern printed on the ceramic substrate, thereby connecting the two conductor patterns.

然しこのような外部結線は望ましい形ではな
く、チツプ上でパターン形成がなされる際にチツ
プ内において導電部分が接続できれば製作工数の
節減に止まらず、バブルメモリの信頼度向上の面
からも寄与が大きい。
However, such external connections are not desirable, and if conductive parts could be connected within the chip when patterns are formed on the chip, it would not only save manufacturing man-hours but also contribute to improving the reliability of bubble memory. big.

本発明はこの点に着目してなされたもので、以
下図面により一実施例を従来例と比較しながら説
明する。
The present invention has been made with attention to this point, and one embodiment will be described below with reference to the drawings while comparing it with a conventional example.

第1図は1/10縮少型投影露光機を用いて従来の
露光マスク又はレチクル(パターンマスク)によ
り1パターンの導体パターンを基板上に形成した
状態を示す図であつて、この例の場合レチクルの
透光部分は横50mm、縦100mmの矩形でその中に導
体パターンの相似拡大パターンである遮光パター
ンが形成されている。
Figure 1 shows a state in which one conductor pattern is formed on a substrate using a conventional exposure mask or reticle (pattern mask) using a 1/10 scale projection exposure machine, and in this example The light-transmitting part of the reticle is a rectangle with a width of 50 mm and a height of 100 mm, and a light-shielding pattern, which is a similar enlarged pattern of a conductor pattern, is formed within the rectangle.

第1図で導電パターン1はゲート回路、発生回
路、センス回路などの導体回路を簡略化して模式
的に示したもので、これはバブル結晶磁性薄膜の
表面に絶縁膜を被着した基板2の該絶縁膜上に形
成されている。又、導体パターン1の製作は、先
づ基板2の絶縁膜全表面に蒸着等でAu等からな
る導体膜を被着させた後、該導体膜上にポジ型レ
ジストを塗膜し、この状態の基板2を露光機に掛
けて所定マスクパターン(導体パターン1と同形
状で10倍のマスクパターン)が形成されたレチク
ルにより露光処理する。この露光にて導体パター
ン1に相当した部分のレジスト膜はレチクルより
透過光が与えられずに未感光状態で、それ以外の
部分は重合して溶解されやすい状態にされる。こ
の後現像処理にて導体膜上に導体パターンに相当
したレジストパターンを形成し、この状態で導体
膜のエツチング処理を行なうことにより導体パタ
ーン1が製作されている。
In Fig. 1, conductive pattern 1 is a simplified schematic representation of conductive circuits such as a gate circuit, a generator circuit, and a sense circuit. It is formed on the insulating film. In addition, the conductor pattern 1 is manufactured by first depositing a conductor film made of Au or the like on the entire surface of the insulating film of the substrate 2 by vapor deposition or the like, and then coating the conductor film with a positive resist. The substrate 2 is placed in an exposure machine and exposed using a reticle on which a predetermined mask pattern (a mask pattern having the same shape as the conductor pattern 1 but 10 times larger) is formed. During this exposure, the portions of the resist film corresponding to the conductor pattern 1 are not exposed to transmitted light from the reticle and remain unexposed, while other portions are polymerized and easily dissolved. Thereafter, a resist pattern corresponding to the conductor pattern is formed on the conductor film by a development process, and the conductor pattern 1 is manufactured by etching the conductor film in this state.

第2図は従来方法に関するもので、これは第1
図のレチクルを用い、先づウエハー基板2上のレ
ジスト膜のA部分に導体パターン1に相当したパ
ターンを投影露光し、続いて該基板2をレチクル
パターンの1幅分(図の場合5mm、以後1ピツチ
と云う)移動させたB部分に再びA部分と同じパ
ターンを投影露光してバブルメモリ1チツプ素子
分のレジスト膜露光を行なう。
Figure 2 relates to the conventional method, which is the first
Using the reticle in the figure, first project and expose a pattern corresponding to the conductor pattern 1 onto part A of the resist film on the wafer substrate 2, then expose the substrate 2 by one width of the reticle pattern (5 mm in the case of the figure, hereinafter The same pattern as that of the A part is again projected and exposed on the moved part B (referred to as one pitch) to expose a resist film for one chip element of the bubble memory.

次に基板2を1ピツチより少し長く(図の場合
5.2mm)移動させてC部分にA,B部分と同じパ
ターンを投影露光することにより次のチツプの片
側部分のパターンを露光する。このようにして、
基板2上のレジスト膜を該基板2の移動により1
チツプ内のパターンを連続に且つ各チツプ間には
所定の隙間を与えて所定数のチツプが得られるよ
うに複数回露光し、この後上述したようにレジス
ト膜の現像処理と導体膜のエツチング処理を行な
うことにより第2図の如く基板2のA,B,C部
分に導体パターン1が形成される。
Next, make the board 2 a little longer than 1 pitch (in the case of the figure)
5.2 mm) and project and expose the same pattern as parts A and B onto part C, thereby exposing the pattern on one side of the next chip. In this way,
The resist film on the substrate 2 is removed by moving the substrate 2.
The pattern inside the chip is exposed multiple times in a continuous manner with a predetermined gap between each chip to obtain a predetermined number of chips, and then the resist film is developed and the conductor film is etched as described above. By doing this, conductive patterns 1 are formed on portions A, B, and C of the substrate 2 as shown in FIG.

こゝでB,C部分の間の点線a…a′はチツプ完
成後に切り出されるウエハー基板上の位置を示し
ている。
Here, the dotted lines a...a' between portions B and C indicate the positions on the wafer substrate that are cut out after the chip is completed.

第3図は切り出されたメモリチツプ3を磁器基
板4上に装着後、基板4上に印刷配線されている
導電パターン5,5′とメモリチツプ3のA,B
部分に形成された導電パターン1,1とをワイヤ
ボンデイング法で結線した従来のバブルメモリ構
造を示している。
FIG. 3 shows the conductive patterns 5, 5' printed and wired on the substrate 4 and A, B of the memory chip 3 after the cut out memory chip 3 is mounted on the ceramic substrate 4.
It shows a conventional bubble memory structure in which conductive patterns 1, 1 formed on the portions are connected by a wire bonding method.

第3図から明らかなように、従来では基板4上
に導体パターン5′を必要とし、且つそれのワイ
ヤ接続処理を行なわなければならずコスト高にな
り、高信頼度のバブルメモリを得ることが難し
い。このような欠点は従来法では第2図で述べた
如く、チツプ内に2群の導電パターンを2度露光
してパターン形成する際、各パターン間をチツプ
内でパターン接続していないことから発生してい
る。
As is clear from FIG. 3, the conventional method requires a conductor pattern 5' on the substrate 4 and also requires wire connection processing, resulting in high cost and making it difficult to obtain a highly reliable bubble memory. difficult. These drawbacks arise from the fact that in the conventional method, when two groups of conductive patterns are exposed twice to form patterns within a chip, there is no pattern connection between each pattern within the chip, as described in Figure 2. are doing.

次に本発明にかかる露光方法を第4図〜第6図
を参照しながら説明する。
Next, the exposure method according to the present invention will be explained with reference to FIGS. 4 to 6.

第4図は本発明にかかるレチクルのマスクパタ
ーン形状を示す図で、これはガラス等の透明基板
表面が透光部分を除き遮光処理されたマスク基板
6からなる。このマスク基板6は従来のレチクル
と同様横50mm、縦100mmの矩形透光部分7を有す
るが、それとは該透光部分7内に位置する導体パ
ターンを得るための遮光パターン8形状が異な
り、且つ透光部分7の左右に四角な小面積からな
る導体パターンの接続切断処理を行なうための透
光部分9,10を有する点で大きく異なる。遮光
パターン8は従来の導体パターン1の形状を基本
とし、その端子部8aから外部へ段差付きの接続
パターン11が導出し、該接続パターン11の端
部が透光部分9,10と一定間隔介し対向してい
る。
FIG. 4 is a diagram showing the shape of a mask pattern of a reticle according to the present invention, which is composed of a mask substrate 6 made of a transparent substrate such as glass whose surface is subjected to a light-shielding treatment except for light-transmitting portions. This mask substrate 6 has a rectangular light-transmitting portion 7 with a width of 50 mm and a length of 100 mm, similar to a conventional reticle, but the shape of a light-shielding pattern 8 for obtaining a conductive pattern located within the light-transmitting portion 7 is different from that. The main difference is that light-transmitting parts 9 and 10 are provided on the left and right sides of the light-transmitting part 7 for connecting and cutting a conductor pattern having a small rectangular area. The light-shielding pattern 8 is based on the shape of the conventional conductor pattern 1, and a stepped connection pattern 11 is led out from the terminal portion 8a to the outside, and the ends of the connection pattern 11 are connected to the light-transmitting portions 9 and 10 at a constant interval. They are facing each other.

なお、このレクチルを用いて投影露光する場合
は、透光部分7以外に透光部分9,10から光が
基板上のレジスト膜に照射され露光される。
Note that when projection exposure is performed using this reticle, the resist film on the substrate is exposed by being irradiated with light from the light-transmitting parts 9 and 10 in addition to the light-transmitting part 7.

第5図は第4図のレチクルを用いて1チツプ用
のレジストパターンを形成する本発明にかかる露
光方法を示すものである。
FIG. 5 shows an exposure method according to the present invention for forming a resist pattern for one chip using the reticle shown in FIG.

図において、露光処理される基板12は従来と
同様バブル結晶磁性薄膜であつて、該磁性薄膜上
に絶縁膜を介して全面にポジ型のレジスト膜が塗
膜されているものとする。本方法は第4図のレチ
クルを用いて、先づ基板12の透光部分7に対応
したA部分のレジスト膜について投影露光し、続
いて基板12をピツチP1、即ち4.95mmと1ピツチ
より僅か少い距離だけ移動させてB部分を投影露
光する。この重複状態での露光は若干の位置ずれ
によりAB部分間でレジストの残り(コンダクタ
ーシヨート)が生ずるのを防ぐためである。
In the figure, it is assumed that the substrate 12 to be exposed to light is a bubble crystal magnetic thin film as in the conventional case, and a positive resist film is coated over the entire surface of the magnetic thin film with an insulating film interposed therebetween. In this method, using the reticle shown in FIG. 4, first, the resist film of the part A corresponding to the transparent part 7 of the substrate 12 is projected and exposed, and then the substrate 12 is exposed to a pitch P1, that is, 4.95 mm, which is slightly less than 1 pitch. Move it a short distance and project and expose part B. The purpose of this overlapping exposure is to prevent resist residue (conductor shot) from occurring between the AB portions due to slight positional deviation.

この場合先のA部分投影露光の際、次に投影露
光されるB部分内のレジスト膜も透光部分9に対
向した9a部が投影露光され、且つ透光部分10
の対向部分10aも露光される。
In this case, during the previous projection exposure of the A part, the resist film in the B part to be projected next is also projected exposed in the part 9a facing the transparent part 9, and the transparent part 10
The opposing portion 10a of is also exposed.

次にB部分の投影露光を行うと、既に露光され
たA部分のレジスト膜は点線で示す10b部が透
光部分10によつて重複露光される。また次に投
影露光されるC部分のレジスト膜は遮光パターン
8の接続パターン11によつて遮光される部分が
透光部分9によつて9b部の如く予じめ投影露光
され感光状態となる。
Next, when the projection exposure of the B part is performed, the part 10b of the already exposed resist film of the A part shown by the dotted line is overlapped by the transparent part 10. Further, in the resist film of the C portion to be projected next, the portion shielded from light by the connection pattern 11 of the light-shielding pattern 8 is exposed by projection in advance by the light-transmitting portion 9 as a portion 9b, and is brought into a photosensitive state.

次にC部分の投影露光は基板12をピツチ
P2、即ち5.15mmと1ピツチより長く従来と同様に
移動させて行うと、B部分内のレジスト膜の未感
光状態の10C部分が透光部分10によつて露光
され、且つ次の部分のレジスト膜の9C部分が透
光部分9によつて露光される。
Next, projection exposure of portion C is performed by pitching the substrate 12.
P2, that is, 5.15 mm, when the resist film is moved longer than 1 pitch in the same way as before, the unexposed 10C part of the resist film in part B is exposed by the transparent part 10, and the resist of the next part is Portion 9C of the film is exposed by transparent portion 9.

こゝで第5図のレジスト膜に投影された遮光パ
ターン8および接続パターン11による未感光状
態のレジストパターン(網目模様部分)を見る
と、A部分とB部分のレジストパターンはその対
向縁部が重複し重複露光が行われているため両パ
ターンは接続されており、一方投影露光された透
光部分9,10による露光部分9a,10bは位
置がずれているため本レジストパターン自体を露
光させない。
Looking at the unexposed resist pattern (mesh pattern part) formed by the light-shielding pattern 8 and the connection pattern 11 projected onto the resist film in FIG. 5, the opposing edges of the resist patterns in parts A and B are Since the two patterns are overlapped and overlapping exposure is performed, the two patterns are connected. On the other hand, the exposed portions 9a and 10b formed by the transparent portions 9 and 10 exposed by projection are out of position, so that the main resist pattern itself is not exposed.

次にB,C部分については1ピツチより僅か離
れて投影露光されているために、B部分投影露光
の際は次に投影されるC部分の接続パターン11
が9b部分の位置で露光される。またC部分投影
の際にはB部分内のレジストパターン(未感光状
態)が10c部分で感光されるため現像した際に
は図示の如く該レジストパターンが10c部分で
切断された形状に描かれる。又A部分内のレジス
トパターンはその前の投影露光時に透光部分9に
より9b部分と同様感光形成された9d部分でも
つて切断状態に形成される。
Next, since portions B and C are projected and exposed slightly more than one pitch apart, during projection exposure of portion B, the connection pattern 11 of portion C that is projected next
is exposed at the position of part 9b. Further, when projecting portion C, the resist pattern (unexposed) in portion B is exposed at portion 10c, so when developed, the resist pattern is drawn in a shape cut at portion 10c as shown in the figure. Further, the resist pattern in the A portion is also formed in a cut state at the portion 9d, which was photosensitively formed by the light-transmitting portion 9 during the previous projection exposure.

そして、このように第4図のレチクルを用いて
基板12上のレジスト膜を露光することにより、
これを現像した際未感光状態のレジストパターン
が第5図の如く基板12の導体膜に残り、該導体
膜をエツチング処理すれば該レジストパターンに
対応した導体パターンが基板12上に絶縁膜を介
して形成される。
Then, by exposing the resist film on the substrate 12 using the reticle shown in FIG. 4 in this way,
When this is developed, an unexposed resist pattern remains on the conductive film of the substrate 12 as shown in FIG. It is formed by

第6図は第5図の本露光方法によつて形成され
たメモリチツプ13を磁器基板14上に装着し、
該磁器基板14の導体パターン15とメモリチツ
プ13の導体パターン16,17とをワイヤボン
デイング接続した本発明にかかるバブルメモリ構
造を示すものである。これは第3図の従来と比較
すれば明らかな如く、導体パターン16と17が
チツプ内でパターン接続されている。
FIG. 6 shows a memory chip 13 formed by the present exposure method shown in FIG. 5 mounted on a ceramic substrate 14,
This figure shows a bubble memory structure according to the present invention in which the conductor pattern 15 of the ceramic substrate 14 and the conductor patterns 16 and 17 of the memory chip 13 are connected by wire bonding. This is clear when compared with the conventional circuit shown in FIG. 3, in which conductor patterns 16 and 17 are pattern-connected within the chip.

第7図および第8図は本露光方法の理解を更に
容易にさせるため、第5図のA,B,C部分の投
影露光によるレジストパターンの接続および切断
部分を拡大した図である。第7図はA,B部のレ
ジストパターン18,19が接続される状態を示
し、斜め右下りの斜線部20はA部分を投影露光
した場合のレジスト未感光領域を、また斜め左下
りの斜線部21はB部分を投影露光した場合の未
感光領域を示し、A,B両部分投影露光後におけ
るレジスト未感光領域は斜交線で表わされるレジ
ストパターン18,19のみであり、透光部分
9,10による感光部はこれよりそれている。
7 and 8 are enlarged views of the connecting and cutting portions of the resist pattern by projection exposure in portions A, B, and C of FIG. 5, in order to further facilitate understanding of the present exposure method. FIG. 7 shows the state in which the resist patterns 18 and 19 in parts A and B are connected, and the diagonally downwardly diagonal lined area 20 to the right indicates the unexposed area of the resist when the A part is exposed by projection. Part 21 shows an unexposed area when part B is exposed by projection, and the unexposed area of the resist after projection exposure of both parts A and B is only the resist patterns 18 and 19 represented by diagonal lines, and the transparent part 9 , 10 deviates from this.

なお両部分ABの重複部22は2重露光されて
いる。
Note that the overlapping portion 22 of both portions AB is double exposed.

次に第8図はB,C部分のレジストパターン1
9,23が切断される状態を示し、斜め右下りの
斜線部24はB部分を投影露光した場合のレジス
ト未感光領域を、また斜め左下りの斜線部25は
C部分を投影露光した場合の未感光領域を示し、
この場合B,C両部分投影露光後におけるレジス
ト未感光領域は斜交線で表わされる部分で、レジ
ストパターン19,23は透光部分9,10によ
り切断されている。
Next, Fig. 8 shows resist pattern 1 of parts B and C.
9 and 23 are cut, the diagonally downward diagonal shaded area 24 represents the resist unexposed area when portion B is exposed by projection, and the diagonally downwardly diagonal shaded portion 25 to the left represents the resist unexposed area when portion C is exposed by projection. indicates an unexposed area,
In this case, the unexposed areas of the resist after the projection exposure of both parts B and C are shown by diagonal lines, and the resist patterns 19 and 23 are cut by the transparent parts 9 and 10.

こゝでB,C部分の境界部26のレジストは感
光されないで残るが、この部分はチツプ切り出し
部分であつて、チツプの特性には影響を及ぼすこ
とはない。
Here, the resist at the boundary 26 between portions B and C remains unexposed, but this portion is a portion from which the chip is cut out and does not affect the characteristics of the chip.

本実施例は従来記憶容量の大きいメモリチツプ
のパターン形成に当つては、同一レチクルを用い
2回隣接して投影露光することにより1チツプの
パターン形成を行い、回路接続が必要な部分はワ
イヤーボンデイングにより行われているが、本発
明を実施する場合は、パターンを1部変更したレ
チクルを用い、投影露光する際の基板移動距離を
1ピツチより変えて行うことにより、両パターン
の回路接続および切断が行われる例を示したもの
である。
In this embodiment, when patterning a memory chip with a large storage capacity, the same reticle is used to perform two adjacent projection exposures to form a pattern for one chip, and wire bonding is used for parts that require circuit connections. However, when implementing the present invention, a reticle with a partially changed pattern is used, and the substrate movement distance during projection exposure is changed from 1 pitch, thereby connecting and disconnecting the circuits of both patterns. This is an example of how this is done.

以上説明したように本発明はホトレジストのよ
うな感光性材料を塗布した基板を移動して露光を
行う露光方式において移動量を変えて露光するこ
とにより、マスクパターンとは異なるパターン形
成を可能とするもので、マスクパターンの節減に
留まらず、信頼度の向上などの点においても効果
は頗る大である。
As explained above, the present invention enables the formation of a pattern different from a mask pattern by changing the amount of movement in an exposure method in which a substrate coated with a photosensitive material such as photoresist is moved and exposed. Therefore, the effect is significant not only in terms of reducing the number of mask patterns, but also in terms of improving reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のレチクルを用いて投影露光した
際の形成導体パターンを示す図、第2図は従来法
による連続露光を行なつて得たバブルメモリチツ
プのパターンの説明図、第3図は従来のバブルメ
モリにおける導電パターン接続を示す図、第4図
は本発明にかかるレチクルのマスクパターンを示
す図、第5図は本発明にかかる露光方法によりバ
ブルメモリチツプのレジストパターンを得る際の
説明図、第6図は本発明にかかるバブルメモリの
導体パターン接続を示す図、第7図と第8図は本
発明にかかる露光法によるレジストパターンを拡
大して示す図である。 符号の説明、1,16,17は導電パターン、
18,19,23はレジストパターンである。
Figure 1 is a diagram showing the conductor pattern formed when projection exposure is performed using a conventional reticle, Figure 2 is an explanatory diagram of the pattern of a bubble memory chip obtained by continuous exposure using the conventional method, and Figure 3 is FIG. 4 is a diagram showing a conductive pattern connection in a conventional bubble memory, FIG. 4 is a diagram showing a mask pattern of a reticle according to the present invention, and FIG. 5 is an explanation of obtaining a resist pattern of a bubble memory chip by an exposure method according to the present invention. 6 are diagrams showing the conductor pattern connections of the bubble memory according to the present invention, and FIGS. 7 and 8 are diagrams showing enlarged resist patterns formed by the exposure method according to the present invention. Explanation of symbols: 1, 16, 17 are conductive patterns,
18, 19, and 23 are resist patterns.

Claims (1)

【特許請求の範囲】[Claims] 1 基板上に被着された感光膜と、光透過領域内
に所定形状のマスクパターンが形成された露光マ
スクとを有し、該露光マスクと前記基板とを相対
的に所定ピツチづつ移動させながら各ピツチ毎に
前記マスクパターンを前記感光膜へ焼付け、且つ
該焼付けマスクパターンにより少なくとも2個の
隣接マスクパターンを1素子分とした素子パター
ンを複数形成してなる露光方法において、前記露
光マスクは第1の前記光透過領域外で且つ前記移
動方向に沿つた両側にそれぞれ第2の光透過領域
を設けて形成し、前記所定ピツチは前記各素子パ
ターン内のマスク移動量をピツチP1、隣合うマ
スク移動量をピツチP2とそれぞれ一定にし、且
つピツチP1よりピツチP2の方を大きく設定し
て、前記マスクパターンを焼き付けた際に、前記
第2光透過領域のそれぞれが1ピツチ前および後
の前記第1光透過領域に対応した部分の前記感光
膜を露光することにより、前記素子パターンを前
記マスクパターンとは異なる形状に形成してなる
ことを特徴とする露光方法。
1 comprises a photoresist film deposited on a substrate and an exposure mask in which a mask pattern of a predetermined shape is formed in a light transmitting region, and while the exposure mask and the substrate are relatively moved by a predetermined pitch. In the exposure method, the mask pattern is printed on the photoresist film for each pitch, and a plurality of element patterns each consisting of at least two adjacent mask patterns are formed by the baked mask pattern, wherein the exposure mask is A second light transmitting region is provided outside the first light transmitting region and on both sides along the moving direction, and the predetermined pitch is a distance P1 of the mask movement within each element pattern, and a second light transmitting region is formed on both sides of the first light transmitting region along the moving direction, and the predetermined pitch is a distance P1 of the mask movement within each element pattern, When the mask pattern is printed with the movement amount being constant with the pitch P2 and the pitch P2 being set larger than the pitch P1, each of the second light transmitting areas is set one pitch before and after the first one. An exposure method characterized in that the element pattern is formed in a shape different from the mask pattern by exposing a portion of the photoresist film corresponding to one light transmission area.
JP18723580A 1980-12-29 1980-12-29 Exposure method Granted JPS57112753A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP18723580A JPS57112753A (en) 1980-12-29 1980-12-29 Exposure method
DE8181306134T DE3173277D1 (en) 1980-12-29 1981-12-24 Method of projecting circuit patterns
EP81306134A EP0055620B1 (en) 1980-12-29 1981-12-24 Method of projecting circuit patterns
US06/333,814 US4408875A (en) 1980-12-29 1981-12-31 Method of projecting circuit patterns

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18723580A JPS57112753A (en) 1980-12-29 1980-12-29 Exposure method

Publications (2)

Publication Number Publication Date
JPS57112753A JPS57112753A (en) 1982-07-13
JPS6233580B2 true JPS6233580B2 (en) 1987-07-21

Family

ID=16202415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18723580A Granted JPS57112753A (en) 1980-12-29 1980-12-29 Exposure method

Country Status (1)

Country Link
JP (1) JPS57112753A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57168250A (en) * 1981-04-10 1982-10-16 Fujitsu Ltd Exposing method
JPS62147728A (en) * 1985-12-23 1987-07-01 Fujitsu Ltd Exposing method
JPS6355550A (en) * 1986-08-26 1988-03-10 Mamiya Koki Kk Divisionally projecting and exposing method for printed board
JPH03116714A (en) * 1989-09-28 1991-05-17 Nec Ic Microcomput Syst Ltd Manufacture of semiconductor integrated circuit element

Also Published As

Publication number Publication date
JPS57112753A (en) 1982-07-13

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