WO1994029902A1

WO1994029902A1 - Flexcell gate array

Info

Publication number: WO1994029902A1
Application number: PCT/US1994/006214
Authority: WO
Inventors: Walter F. Bridgewater
Original assignee: National Semiconductor Corporation
Priority date: 1993-06-07
Filing date: 1994-06-03
Publication date: 1994-12-22
Also published as: KR960702947A; JPH09507000A; EP0702849A1

Abstract

Novel gate arrays incorporate simple, but ingenious architectural features. A programmable layer of polycrystalline silicon is utilized to improve logic and RAM densities. The programmable layer of polycrystalline silicon is capable of providing electrical connections within a particular logic cell, without requiring the use of electrical interconnections within a dedicated routing channel. This allows increased density of the gate array. By providing programmable polycrystalline silicon, polycrystalline silicon contact connections are placed only where needed, avoiding the need to leave space between adjacent polycrystalline silicon lines for all potential contact connections.

Description

FLEXCEL GATE ARRAY

Background

This invention pertains to integrated circuits, and more particularly to gate array architectures in which an array of electronic gates are fabricated in a base array, and which are then programmed utilizing personalization layers in order to provide a specific function.

In prior art sea-of-gates architectures, as described for example in U.S. Patent No. 4,884,118, one layer of metallization interconnect is used for connecting transistors to form more complex logic gates. To make these connections possible, metal contact sites are needed between each transistor, in order to provide the possibility of making each possible connection. This results in a significant amount of integrated circuit surface area which is dedicated solely to the possibility of forming a metal contacts for interconnect purposes. Such prior art sea-of-gates architectures must resort to a third layer of metal to achieve densities on the order of 100,000 gates, resulting in a more complex, and thus expensive, fabrication process.

In typical prior art gate arrays, bonding pads are fixed when the base array is laid out, thus requiring a redesign of the base array if it is desired to place a device into a different package type, having a different lead frame layout. Alternatively, the input/output (I/O) cells are fixed in the array, and the bonding pads may be placed as desired, with appropriate metallization interconnects made between the bonding pads and their associated I/O cells.

U.S. Patent No. 4,893,170 describes an integrated circuit in which a plurality of interconnect layers are utilized. At least one of the interconnected layers runs in a vertical direction along the surface of the integrated circuit, and the remaining interconnect layers run in a horizontal direction on the surface of the integrated circuit device. Generally, due to potential problems with congestion, alternate levels of electrical interconnects run perpendicular to each other. The 170 patent describes that either first and second layers of vertical interconnects or first and second layers of horizontal interconnects are used to connect to the input terminals and output terminals, respectively, of the various logic cells contained within the gate array. In the '170 patent, one layer of polycrystalline silicon is used to form the gate electrodes of MOS transistors within the logic cells of the gate array, and also serves to provide electrical interconnection between the logic cells and the metal layers of electrical interconnection located in a dedicated routing channel. U.S. Patent No. 4,602,270 describes a gate array in which the locations for contacts between the underlying silicon and a polycrystalline silicon layer, or between the polycrystalline silicon layer and the first layer of interconnect metallization, are predefined, although the actual use of a contact in a predefined location is dependent on the electrical function to be performed by a particular gate array.

U.S. Patent No. 4,811,073 describes a gate array which contains one or more power supply buses encircling the core of the gate array and within the region defined by the I/O cells. The power lines contained within the core of the array are connected to the power supply bus rings, as are the power supply connections to the I/O cells. In this manner, the pitch of the I/O cells and the pitch of the cells within the core of the gate array need not be identical.

U.S. Patent No. 4,809,029 describes a gate array which includes a plurality of I/O cell regions, each having an associated general purpose cell array region. The I/O general purpose cell arrays can be used for fabricating logic particularly useful with a given I/O circuit, for example for testing purposes.

SUMMARY OF THE INVENTION In accordance with the teachings of this invention, novel gate arrays incorporate simple, but ingenious architectural improvements over prior art gate arrays, including prior art sea-of-gate arrays. A programmable layer of polycrystalline silicon is utilized to improve logic and RAM densities as compared with prior art gate arrays which utilize a similar number of metallization layers such that either vertically or horizontally oriented layers of metallization are used to make electrical contact to the input and/or output terminals of gate array cells. The programmable layer of polycrystalline silicon is capable of providing electrical connections within a particular logic cell, without requiring the use of electrical interconnections within a dedicated routing .channel. This allows increased density of the gate array. As an example, in accordance with the teachings of this invention, a gate array is fabricated utilizing two layers of metallization having densities comparable to that which is sometimes capable of being achieved utilizing prior art gate arrays utilizing three layers of metaltization. Similarly, the teachings of this invention provide gate arrays utilizing three layers of metallization which have densities comparable to prior art gate arrays which would require four layers of metallization.

Constructing gate arrays in accordance with the teachings of this invention also provides the highest RAM densities available in a gate array architecture. By providing programmable polycrystalline silicon, polycrystalline silicon contact connections are placed only where needed, avoiding the need to leave space between adjacent polycrystalline silicon lines for all potential contact connections. This results in approximately as 2:1 reduction in cell size.

In accordance with the teachings of this invention, transistors in the gate array are packed closer together than taught in the prior art as a result of the use of a programmable polycrystalline silicon layer. The dedicated space needed for contact sites that are necessary in prior art sea-of-gate arrays is not required. This allows for more logic and higher gate densities for a given process geometry and a given number of metallization layers.

In one embodiment of this invention, gate arrays are fabricated which accommodate mask programmable pad pitches (spacing between bonding pads), tailored for tape automated binding (TAB), gold, or aluminum bonding.

BRIEF DESCRIPTION OF THE DRAWINGS Figure la is a schematic diagram of a prior art 5- input NAND gate;

Figure lb is a layout of the circuit of Figure la utilizing the prior art sea-of-gates technology;

Figure lc is a plan view depicting the layout of the circuit of Figure la in accordance with one embodiment of this invention;

Figure 2 is a plan view of a portion of a gate array structure constructed in accordance with the teaching of this invention;

Figure 3a is a plan view depicting a RAM cell laid out utilizing the prior art sea^'-of-gates technology; Figure 3b is a plan view depicting the layout of one embodiment of a RAM cell constructed in accordance with the teachings of this invention;

Figure 4 is a plan view of a portion of a gate array constructed in accordance with the teachings of this invention; Figure 5 is a plan view of a portion of a gate array constructed in accordance with the teachings of this invention;

Figure 6 is a plan view depicting certain features of the I/O structure in accordance with the teachings of this invention; and

Figure 7 is a plan view depicting certain features of the I/O structure and other features of one embodiment of this invention.

DETAILED DESCRIPTION

In accordance with the teachings of this invention, a gate array is taught which includes a plurality of pairs of diffusion strips, each pair including an N and a P diffusion strip. The N and P diffusion strips are laterally separated by an interdiffusion track. Dedicated routing channels are provided adjacent each diffusion strip opposite the interdiffusion track. One or more cells are formed within a pair of diffusion strips and the associated portion of the interdiffusion track, each cell performing a desired electrical function. A cell is formed by determining the number of polycrystalline silicon gate electrodes required to form the necessary number of transistors to implement the electrical function. These polycrystalline silicon gate electrodes are then placed with minimum spacing, only leaving sufficient room for contacts where it is known they will be specifically needed. If desired, each cell is terminated on each end in a portion of the diffusion regions which are connected to a source of power, such diffusion isolation regions being shared by two adjacent cells, if desired. The diffusion strips are then formed, using the polycrystalline silicon as a partial mask, providing self aligned source/drain regions. In this manner, cells are formed as part of the personalization process, each cell consuming a minimum amount of the length of the diffusion strips. Unlike prior* art gate arrays, dedicated transistors are not formed prior to personalization. RAM cells are formed in a similar manner, but need not be terminated in isolation diffusion regions within the RAM, so that word lines and/or bit lines are conveniently formed. Gate arrays constructed in accordance with the teachings of this invention provide distinct advantages over prior art gate array architectures, including prior art sea-of-gate architecture, particularly with respect to gate utilization. Prior art sea-of-gates architectures typically achieve gate utilizations on the order of 40 percent. In contrast, gate arrays constructed in accordance with the teachings of this invention, depending on the specific circuit design desired by the end user, achieve gate utilization of between approximately 50 percent and 80 percent. To improve gate utilization, in accordance with the teachings of this invention a layer of polycrystalline silicon is used not only for the purposes of forming gate electrodes or providing electrical connection between a gate array cell and a routing channel, as is known in the prior art, but also for providing a certain amount of routing within a gate array cell without requiring the use of dedicated routing channels within which transistors cannot be formed. One embodiment of this invention contains 250K gross gates. This array could, for example, accommodate a design of 58K gates of logic and another 59K bits of RAM. This is equivalent to 164K usable gates. In one embodiment of this invention, gate arrays are fabricated using a 0.8 micron L-effective, ( 1-micron drawn) CMOS process .

In another embodiment of this invention, devices are fabricated using a library of cells common to gate arrays as well as standard cells fabricated from a standard cell library. This library includes a large number of core macros (i.e. large cells performing relatively complex electrical functions), small scale integration (SSI), and medium scale integration (MSI) functions, a variety of different I/O cells, and can be integrated with module-generated, high-density ROM and RAM.

Utilizing a layer of polycrystalline silicon to achieve at least part of the programming required when fabricating a gate array overcomes the need for leaving space for electrical contacts between polycrystalline silicon gate electrodes when they are not needed. Thus, transistors forming the gate array are more closely packed together in accordance with the teachings of this invention, as compared with the prior art gate arrays. For example, Figure la is a schematic diagram of a typical prior art 5-input NAND gate. The interconnection between source/drain regions of numerous transistors, indicated by the arrows in Figure la, do not require connection to metallization interconnects. This fact is lost on the typical prior art layout (shown in Figure lb) of the circuit of Figure la. The layout shown in Figure lb includes space for all possible contacts, thereby wasting a significant amount of area. In contrast, the layout depicted in Figure lc, made in accordance with the teachings of this invention, provides programmable polycrystalline silicon strips 9 which serve as gate electrodes having minimum spacings in areas 10 and 11 where contacts are not needed.

Larger spacing 12 is used in the area where contact 13 is required. As can be seen from a comparison of the prior art layout of Figure lb and the layout in accordance with the teachings of this invention of Figure lc , implemented in accordance with the teachings of this invention is contained in approximately one third of the area of the same gate implemented in a prior art sea-of-gate array, for a given geometry.

Figure 2 is a composite view of one example of an electronic circuit constructed from a portion of gate array core in accordance with the teachings of this invention. Gate array circuit 100 includes P+ diffusion strip 101 and N+ diffusion strip 102. A plurality of polycrystalline silicon gate electrodes 105 are formed within P+ diffusion strip and N+ di fusion strip 102 such that a plurality of transistors are formed therein. As is well known in the art, polycrystalline silicon gate electrodes are fabricated prior to formation of diffusion 101 and 102, thereby providing source/drain regions such as regions 106 and 107 which are self aligned to their associated polycrystalline silicon gate electrodes. If desired, P+ diffusion strip 101 is made wider than N+ diffusion strip 102 in order to match the speed of the N channel and P channel transistors.

P+ diffusion contact 103 and N+ diffusion contact 104 are used to provide electrical interconnection between desired portions of diffusion strips 101 and 102. In the embodiment of Figure 2, N+ diffusion contacts 103 serve to electrically connect desired portions of diffusion strip 101 to supply voltage VDD through a first layer of metallization 110, such as aluminum or an alloy thereof. In an alternative embodiment, metallization 110 is formed of tungsten or an alloy thereof, which provides greater planarity which allows stacked vias to be placed over contacts. Similarly, N+ diffusion contacts 104 are used to connect desired portions of N+ diffusion strip 102 to supply voltage VSS through first layer metallization 111.

Of importance, in accordance with the teachings of this invention various portions of gate array circuitry 100 are electrically interconnected by the use of programmable polycrystalline silicon interconnects which do not need to leave the cell area itself. Thus, for example, polycrystalline silicon interconnect 108 serves to electrically connect two adjacent polycrystalline silicon gate electrodes within N+ diffusion strip 102. Similarly, for example, polycrystalline silicon interconnect 109 serves to electrically connect two polycrystalline gate electrodes within N+ diffusion strip 102 with two polycrystalline silicon gate electrodes within P+ diffusion strip 101. In. contrast to the prior art use of polycrystalline silicon as a programmable interconnect within the gate array, in accordance with the teachings of this invention, the polycrystalline silicon need not exit the cell region itself for location within dedicated routing channel 120 which, in the prior art, would then be used to interconnect the polycrystalline silicon to a metallization interconnect layer. Thus, in accordance with the teachings of this invention, a polycrystalline silicon interconnect is used within the cell area itself, thereby reducing the need for metallization interconnects over the cell, thus allowing this area to be used for intercell routing. By using polycrystalline silicon for interconnection of cell transistors within a cell, metal 1 and metal 2 routing resource utilization is greatly reduced as compared to the prior art. This allows routing intercell connections over the cells with far less congestion, thus freeing up metal 1 routing resource for connecting together larger logic elements, such as gates and flip flops. Metal 1 routes run generally horizontally over the cells (i.e., in locations 118-1 through 118-5) and metal 2 routes run generally vertically across them (i.e., in locations 119-1 through 119-5). If metal 1 is used for making all connects between transistors and gates (as in the prior art), less of the metal 1 interconnection resource is available for longer routes going over the cells. Also shown in the embodiment of Figure 2 are substrate/well contacts 112 and 113, which allow VDD bus 110 to be connected to N well substrate and VSS bus 111 to be connected to P substrate, respectively. As shown in Figure 2, a plurality of substrate/well contacts 112 and 113 are capable of being provided, although selected ones may be eliminated in order to provide room for polycrystalline silicon interconnects beneath power busses 110 and 111 if desired, thereby further- increasing the ability to route within the cell itself rather than requiring dedicated rotating channels 120 or further consuming routing resources within the cell. For example, as shown in Figure 2, polycrystalline silicon interconnect 121 may be used, if desired, to interconnect two polycrystalline silicon gates within P+ diffusion strip 101. Polycrystalline silicon interconnect 121 lies beneath first layer metallization VDD bus 110, which is fabricated to be relatively wide in order to have sufficient current carrying capacity. In the event polycrystalline silicon is routed in the area beneath the power busses, in order to ensure adequate spacing between polycrystalline silicon interconnect 121 and diffusion contacts 112, a number of possible diffusions contacts 122 are simply not formed, thereby preventing inadequate distance between polycrystalline silicon interconnect 121 and contacts 112. Since a large number of possible contacts 112 and 113 are capable of being provided, the elimination of a relatively small number of contacts 112 and 113 in order to allow the placement of polycrystalline silicon interconnects beneath metallization power busses 110 and 111 poses no problem with respect to adequate electrical contact to underlying well and substrate regions. Providing sufficiently wide metallization traces such as busses 110 and 111 has several advantages. In addition to being sufficiently wide to route polycrystalline silicon beneath, it is sufficiently large to allow contact from the second (or higher) level of metallization at any location along its length, and without the need for freeing areas beneath the first layer of metallization. This is particularly true with the enhanced planarity afforded by utilizing tungsten as the first level of metallization. Another advantage of routing relatively wide power busses 110 and 111 is that they are thus highly scalable in that power scales at a factor less than geometry. Thus, by providing ample current carrying capability, the power busses may be scaled geometrically and still have sufficient current carrying capability.

Also shown in the embodiment in Figure 2 is electrical interconnect 114 fabricated from a first layer of metallization. Metallization interconnect 114 serves to electrically connect source/drain region 107 lying within N+ diffusion strip 102 with a similar source/drain region lying within P+ diffusion strip 101, through first layer metallization to diffusion contacts 115. First layer metallization interconnect 114 is also shown connected to metallization via 117, in the event a second layer of metallization (not shown) is to be electrically connected to first layer metallization interconnect 114. Thus, in accordance with the teachings of this invention, inputs and outputs to a cell may be provided to either first or second metallization.

A plurality of potential first layer metallization routing paths 118-1 through 118-5 lie within cell 100 above P+ diffusion strip 101. A similar set of unnumbered potential first layer metallization routing channels exist overlying N+ diffusion strip 102. These potential routing channels run in a horizontal direction, although first layer metallization is capable of being fabricated in either a horizontal or vertical direction. By striving to keep first layer metallization interconnects running in the horizontal direction overlying diffusion strips 101 and 102τ routing density is enhanced. It is shown by the embodiment of Figure 2 that the use of polycrystalline silicon interconnects for routing within the cell, rather than simply for making entry into dedicated routing channel 120, minimizes the consumption of routing resources within dedicated routing channel 120. Similarly, by allowing the use of polycrystalline silicon interconnects within the cell region, as taught by this invention, the consumption of first layer metallization routing resources is also minimized. The available first layer metallization routing paths 118-1 through 118-4 (first layer metallization routing path 118-5 being utilized by first layer metallization interconnects 123 and 124), are available for other first layer metallization interconnects which might be useful, for example for interconnecting other cells within the larger gate array. This further reduces the need for utilizing the resources of dedicated routing channel 120. By providing programmable polycrystalline silicon, interdiffusion track 147 is capable of being used to make contact to polycrystalline silicon regions. As an example, shown in the embodiment of Figure 2 is first layer metallization to polycrystalline silicon contact 116. Similar polycrystalline silicon contacts can be used for connection to levels of metallization higher than the first layer of metallization. It is also possible to make contact to polycrystalline silicon over diffused regions 101 and 102, although this has the disadvantage of increasing capacitance.

Another feature of this invention is also depicted in the plan view of Figure 2. Figure 2 depicts the layout of a cell within long strips 101 and 102 of diffusion which extends beyond cell 100 shown in Figure 2. Cell 100 is terminated on either end by isolation diffusion regions making connection to power. For example, isolation diffusion region 106 is connected to power bus 111 through contact 104. This serves -to provide electrical isolation between cell 100 and adjacent cells, which are formed on either side of cell 100, as diffusion strips 101 and 102 extend beyond cell 100. Increased density is afforded in accordance with the teachings of this invention by allowing adjacent cells to share in terminating diffused area 106, for example.

Another unique feature of the present invention is the use of small routing channels (such as routing channel 120) for greatly increased routeability. As an example, polycrystalline silicon stub 148 extends from within the cell, beneath power bus metallization 110, into routing channel 120. There it is connected to first level metallization interconnect 150 through via contact 149. As shown in Figure 2, a substrate contact 112 is not formed beneath polycrystalline silicon stub 148. Polycrystalline silicon has a higher impedance than metal and thus stub routes are limited to no more than, for example, approximately 50 microns. This minimizes the delay associated with polycrystalline silicon RC time constant.

To quantify the benefits of the present invention from a gate utilization point of view, a benchmark design with worst case requirements for routing resources was utilized. The design contained a large amount (60,000 gates) of low level logic, such as NAND and NOR gates, and wide buses. The comparison was made between the routing resources available on a prior art 2-layer metal sea-of-gates array, a prior art 3-layer metal sea-of-gates array, and a 2-layer metal array constructed in accordance with the teachings of this invention. All other things were equal in the comparison, such as the router, design rules, etc. Implementing the design using a prior art 2-layer metal sea-of-gates array required an integrated circuit die with 576 mils on a side. Using a prior art 3-layer metal sea-of-gates array, with the additional routing resource provided by the third metal layer, reduced the required integrated circuit die size to 487 mils on a side. In contrast, utilizing a 2-layer metal gate array constructed in accordance with the teachings of this invention required an integrated circuit die of only 457 mils on a side. This amounts to a 37 percent improvement in integrated circuit die area as compared with a prior art 2-layer metal sea-of-gate device, without an increase in process complexity. This also amounts to a 12 percent improvement in integrated circuit die size as compared with a prior art 3-layer metal sea-of-gate device, but also includes a rather significant advantage of a much simpler process utilizing one less metallization layer.

To serve the needs of increasingly dense designs on a single chip, one embodiment also provides on-chip

RAM. An improvement of approximately 2:1 in density of RAM is gained over prior art sea-of-gates architectures. This is readily seen by comparing the RAM cell layout of Figure 3a utilizing the prior art sea-of-gates technology, as compared with the embodiment of Figure 3b, which depicts the layout of a RAM cell constructed in accordance with the teachings of this invention. Unlike so-called structured arrays which have a handpacked block of RAM of pre-determined size, in accordance with this invention, RAM is implemented with the same base cell as surrounding logic, allowing complete flexibility in RAM width, depth, the number of RAMs, and their location within the integrated circuit. This also improves the packing density of logic and increases the amount of RAM possible within a gate array of a given physical size.

In addition to density, the other requirement placed on RAM in gate arrays is speed performance. Capacitance of the diffusion area connected to the word line of a RAM memory impacts performance. As discussed above, in accordance with the teachings of this invention, polycrystalline silicon is programmed, and thus the size of the diffusion area can be minimized. As shown in Figure 3b, polycrystalline silicon can be patterned to closely surround a contact (such as contact 307), thereby minimizing diffusion area capacitance. This results in a reduction in the capacitance on the word line, and thus the speed of the RAM is improved. This provides a significant performance advantage as compared with RAM provided in prior art sea-of-gate arrays that have fixed diffusion areas large enough to accommodate multiple possible contacts. In accordance with the teachings of this invention, fabrication processing is considerably simpler as compared with prior art fabrication processes. Table 1 shows a process comparison between National Semiconductor's double layer metal process, a typical prior art double layer metal process, a typical prior art three layer metal process, a typical prior art standard cell device, and the present invention. The "X"s indicate the number of process steps which must be performed following the first process step pertaining to personalization of the device, and the asterisks indicate such process steps which are not themselves personalization steps.

TABLE 1 PROCESS COMPARISONS

National i Semiconductor Prior Art Prior Art Prior Art Prior Art

Process Double Layer Double Layer Three Layer Present Standard Step Metal Metal Metal Invention Cell ell X

Field X

Active X

Poly X X

LDD X* X

N+ X* X

P+ X* X er. Contact X X X X

Metal 1 X X X X X

Via 1 X X X X X

Metal 2 X X X X X

Via 2 X

Metal 3 X

Pad X* X* X* X* X

Total Process Steps 4 5 7 12 Total Programmed Masks 3 4 6 12

In accordance with one embodiment of the present invention, a novel I/O design is utilized which solves a significant cause of poor performance on printed circuit boards. I/O on most prior art gate arrays are TTL- compatible. TTL sinks more current than it sources, which can lead to impedance mismatches on printed circuit board routes. By contrast, one embodiment of the present invention includes output buffers that are optimized to drive terminated printed circuit board traces of specified impedances to provide good transmission-line driving characteristics. In accordance with one embodiment of this invention, I/O buffers are designed and fabricated in order to source and sink the same amount of current. This gives improved waveform characteristics when the gate array is mounted on a printed circuit board for use in a system.

As with prior art gate array, I/O pins are programmable as input/output, bidirectional, power and ground. In addition, in one embodiment of this invention, a gate array is provided having both normal and slew rate controlled outputs. The slew rate controlled outputs are slower but allow more outputs to switch simultaneously, a good feature on designs with wide buses. Slew rate controlled outputs are also well suited for designs that are I/O limited and cannot afford many power pins. Slower slew rates produce less di/dt at the power pins, and therefore less power, supply noise.

In one embodiment, novel gate arrays are provided which also include small I/O gate arrays associated with one or more I/O pins. In one embodiment, such I/O gate arrays are capable of providing approximately 70 transistors, in the same manner as taught with regard to the gate array in the core of the device. These I/O gate arrays allow the designer to implement test circuitry and methods, for example IEEE 1149.1 Joint Test Action Group (JTAG) boundary scan, without using gates i.n the core of the array. The I/O gate arrays are intended specifically for implementing testing features such as boundary scan, and do not detract from the availability of resources in the core of the device. Thus, the designer need not consume core resources when implementing boundary scan. In the event one or'more cells associated with I/O pins are not used for purposes associated with I/O (i.e. testing), those cells are available for use to supplement the functions performed by the core cells. Figure 4 is a plan view depicting the layout of another portion of a gate array constructed in accordance with the teachings of this invention. Shown in Figure 4 are, for example, diffusion strips 619-1 through 619-4, routing channels 620-1 and 620-2 and interdiffusion track 621. Intracell polycrystalline silicon routing trace 601 is located beneath power bus 614 in a region free from substrate contact 615. Cell 600 includes a number of transistors defined by polycrystalline silicon and associated source/drain regions within diffusion strips 619-2 and 619-3. Cell 600 is terminated on each end by diffusion isolation regions 627-1 through 627-4, which are connected to either power bus 614 or 624. Polycrystalline stub connector 602 extends into routing channel 620-2 for connection through contact 603 to second layer metallization 605, which in turn is connected through via 630 to first layer metallization interconnect 631. First layer metallization interconnects such as interconnect 632 are routed within interdiffusion track 621, for example, connection to polycrystalline silicon within the cell through contact 606.

Figure 5 is a plan view depicting another portion of a gate array 700 constructed in accordance with the teachings of this invention, with numerical designations corresponding to similar features in the embodiment of

Figure 4. Of interest, gate array 700 includes cell 780 and cell 781, both formed from portions of diffusion strips 719-2 and 719-3, and each of which are terminated with diffusion isolation regions connected to one of the power busses. Also of interest, cells 780 and 781 are defined by the personalization process, and each transistor within cells 780 and 781 are defined to be of minimum size by the placement of polycrystalline silicon as a step in the personalization process. Space for contacts is provided only where it is certain a contact is needed in order to provide the electrical interconnections required to achieve the electrical function of each cell. Thus, the εize of each cell, i.e. the amount of the length of diffusion strips 719-2 and 719-3 consumed by each cell, is specifically provided as the minimum required to achieve the electrical function of each cell. Figure 6 is a plan view depicting one embodiment of this invention showing a basic I/O structure 200 located adjacent to edge 201 of the integrated circuit die. Associated with bonding pad 202 is N channel I/O array 203 and P channel I/O array 204. N channel I/O array 203 includes a plurality of polycrystalline silicon gates 207 formed within N+ diffusion strips 205-1 through 205-2. As is well known in the art, polycrystalline silicon gate electrodes 207 are formed prior to the diffusion of N+ diffusion strips 205-1 and 205-2, thereby forming source/drain regions 209-1 and 209-2 which are self aligned to their associated polycrystalline silicon gate 207. P channel I/Θ array 204 is fabricated in a similar fashion. Of importance, N channel I/O array 203 and P channel I/O array 204 are fabricated such that their diffusion strips 205-1, 205- 2, 206-1, 206-2 are substantially perpendicular to edge 201 of the integrated circuit and thus their polycrystalline silicon gate electrodes 207 and 208 are substantially parallel with edge 201 of the integrated circuit. In this manner, any desired number of transistors may be fabricated in N channel I/O array 203 and P channel I/O array 204 simply by increasing their length inward from edge 201 of the integrated circuit. While this consumes substantially the same integrated circuit die area as if oriented differently, it does not effect the pitch associated with I/O structure 200. This is a serious drawback in the prior art when utilizing dedicated I/O arrays which are oriented^" perpendicular to the dedicated I/O arrays taught by this invention. In such prior art circuits, increasing the number of transistors in the N channel or P channel I/O arrays necessarily and undesirably increases the pitch of the I/O structure.

While the embodiment of Figure 6 shows two diffusion strips associated with each of N channel I/O array 203 and P channel I/O array 204 any desired number of diffusion strips can be formed within I/O arrays 203 and 204. Similarly, I/O arrays 203 and 204 can be located side by side so long as their combined widths provide an acceptable I/O pitch. Also, not shown for the sake of simplicity in Figure 6, are N channel and/or P channel transistors used for constructing the actual I/O buffer circuitry, as well as electrostatic discharge (ESD) protection, as is well known in the art.

Figure 7 is a plan view of portion of a gate array constructed in accordance with the teachings of this invention, again generally depicting the bonding pads and I/O structure. Gate array 300 includes a plurality of bonding pads 202 and their associated I/O buffers 519. In the interior of gate array 300 lies logic core 303. Also shown in Figure 7 are N channel diffusion strips 203-1 and 203-2, and P channel diffusion strips 204-1 through 204-2. These are used for forming gates associated with bonding pad 202, as previously described with regard to the embodiment of Figure 6. Of interest, the pitch associated with I/O buffer 519 is substantially equal to the pitch associated with bonding pad 202, as well as the pitch associated with diffusion strips 203-1, 203-2, 204-1, and 204-2. By arranging the transistors within I/O buffer 519 in the same orientation as previously described with regard to the I/O array, transistors formed within the diffusion strips, additional transistors may be formed within I/O buffer 519 by increasing the depth of I/O buffer 519 rather than its width, thereby not increasing its pitch. Also shown in the embodiment of Figure 7 are ^"the power connections to I/O buffer 519. In this embodiment, I/O buffer 519 is formed symmetrically with respect to its power in that one VSS connection 527 is located along its central axis having a size sufficient for the power needs of I/O buffer 527. Two VDD power connections 526 are provided on either edge of I/O buffer 519, thereby collectively providing sufficient VDD power capacity to I/O buffer 519. VDD power connections 526 of adjacent I/O buffer 519 abut, and thus are contacted by a single metallization layer. In the embodiment shown in Figure 7, the power busses (not shown) which contact VSS terminal 527 and VDD terminals 526 are also capable of being extended over the abutting edges of diffusion strips 204-1 and 204-2; and 203-1 and 203-2 (of adjacent I/O gate arrays), respectively. This allows for convenient routing of power to both I/O buffers 519 and the I/O gate arrays. Furthermore, since the power connection to I/O cells 519 are symmetrical with respect to its central axis, the VSS and VDD power busses may extend to the other edge of the die and connect to their counterparts in the I/O buffers on the opposite edge of the integrated circuit. As previously described with reference to Figure 2, the same power busses which extend over the core of the gate array in order to connect to I/O buffers on opposite edges of the integrated circuit can also be used to connect to the first layer metallization power busses within the various cells of the gate array. This obviates the need for a dedicated power routing ring around the core of the array just interior of the I/O circuitry, providing a significant savings in integrated circuit area. This is accomplished while requiring a single layout for the I/O circuitry, since it is symmetrical with respect to its power access.

In accordance with the teachings of this invention, the normally unused space 304 near the corners of the integrated circuit is put to use. In one embodiment, vertical PNP transistors are fabricated in region 304. Vertical PNP transistors are capable of being fabricated during an MOS fabrication process without additional process steps . These vertical PNP transistors are capable of being used for any desired purpose, including their use to form bandgap voltage references, which are particularly useful when implementing analog functions in gate array 300.

As another feature available in accordance with the teachings of this invention, because the polycrystalline silicon layers are programmable (as described previously with regard to Figure 2), transistors are capable of being provided having programmable gate lengths. This is particularly useful for forming analog functions, where current ratios are of importance and are easily provided as a function of ratios of gate lengths of various transistors. Furthermore, since the polycrystalline silicon layer is programmable, diffused resistors can be provided, including matched sets of diffused resisors, which are also useful in analog functions. Furthermore, the fused regions can, if not otherwise diffused, be used to fabricate diffused resistors, also useful in performing analog functions. Additionally, by utilizing programmable polycrystalline silicon in accordance with the teachings of this invention, capacitors are easily fabricated of desired capacitances by fabricating a polycrystalline silicon layer of a desired size over a diffused area, with the polycrystalline silicon serving as one plate of the capacitor and the diffused region serving as the other plate of the capacitor.

Appendix A to the specification is a document outlining certain features of the claimed invention Appendix B is a gate array design manual which also describes certain features of the present invention. Appendix C is additional information describing certain features of this invention. All publications and patent applications are herein incorporated by reference to the same extent as if each individual publication or patent application was specifically and individually indicated to be incorporated by reference. The invention now being fully described, it will be apparent to one of ordinary skill in the art that many changes and modifications can be made thereto without departing from the spirit or scope of the appended claims .

Claims

WHAT IS CLAIMED IS:

1. A semiconductor gate array device, having a top surface, comprising: a plurality of cells, each having at least one transistor; one or more vertical wirings, each of which is contained in a wiring layer which generally runs in a vertical direction along said surface; one or more horizontal wirings, each of which is contained in a wiring layer which generally runs in a horizontal direction along said surface; and a polycrystalline silicon layer which serves to provide gate electrodes to said plurality of cells and which serve^'s as a programmable first wiring layer for providing electrical interconnections within at least one of said plurality of cells.

2. A semiconductor device as in claim 1 wherein said polycrystalline silicon layer is formed to have minimum spacing between at least some of adjacent ones of said gate electrodes, and is formed to have larger spacing where contact is made to a region underlying and between two adjacent portions of said polycrystalline silicon layer.

3. A semiconductor device as in claim 2 which further comprises at least two diffused strips^separated by an interdifusion track, wherein programmable contacts to said polycrystalline silicon layer are made within said interdiffusion track.

4. A semiconductor device as in claim 2 which further comprises: at least two diffused strips separated by an interdiffusion track; a routing channel formed adjacent to one of said diffused strips on the side opposite said interdiffusion track; and at least one polycrystalline stub connector extending from above at least one of said diffused strips and into said routing channel.

5. A semiconductor device as in claim 4 which further comprises: a conductive power bus formed above a portion of the width of said first diffused strip and a portion of the width of said routing channel; and at least one polycrystalline silicon connector located beneath said conductive power bus and running at least partially along the length of said conductive power bus, said polycrystalline silicon connector making electrical contact to at least one location within a cell.

6. A semiconductor device as in claim 5 which further comprises a plurality of locations for the formation of substrate contacts to said power bus, said substrate contacts- not being formed at those ones of said plurality of locations which are less than a predetermined distance from said polycrystalline silicon connectors or said polycrystalline silicon stub connectors .

7. An MOS gate array device comprising one or more vertical PNP transistors.

8. A gate array as in claim 7 wherein said PNP transistors are interconnected to form a band gap voltage reference.

9. A device as in claim 1 which further comprises : at least one pair of MOS transistors having their channel widths, as defined by their polycrystalline silicon gate electrodes, of a desired ratio.

10. A device as in claim 9 wherein said desired ratio is a function of a desired current carrying ratio of said pair of MOS transistors.

11. A device as in claim 1 which further comprises at least one capacitor having as its first plate a portion of one of said diffusion strips, and as its second plate a portion of said polycrystalline silicon layer, the sizes of said plates being programmable to provide a desired capacitance value.

12. A device as in claim 1 which further comprises at least one polycrystalline silicon resistor formed from said layer of polycrystalline silicon.

13. A device as in claim 1 which further comprises at least one diffused resistor formed from at least portions of either or both of said diffusion strips.

14. A gate array comprising: a core including a plurality of cells; a first I/O cell located near a first edge of said gate array and having a longitudinal centerline generally perpendicular to said first edge; and a second I/O cell located near a second edge of said gate array generally opposite said first edge and having a longitudinal centerline generally perpendicular to said second edge, each of said first and second I/O cells comprising: a first power terminal located about said longitudinal center line of said I/O cell; and a set of second power terminals symmetrically spaced apart from said first power terminal; a first power bus extending across said gate array and making contact with said first power terminals of said first and second I/O cells; and a second power bus extending across said gate array and making contact with one terminal of said second set of power terminals of said first I/O cell and the other terminal of said second set of power terminals of said second I/O cell.

15. A gate array as in claim 14 which further comprises a third I/O cell located adjacent said first I/O cell, wherein said power terminals of second set of power terminals are located at the edge of said I/O cells such that one terminal of said second set of power terminals is located adjacent to the other terminal of said second set of power terminals.

16. A gate array as in claim 15 wherein said second power bus is in contact with said one terminal of said second set of power terminals of said first I/O cell and said other terminal of said second set of power terminals of said third I/O cell.

17. A gate array as in claim 14 wherein the current carrying ability of said first power connection is approximately equal to the sum of the current carrying ability of said second set of power connections .

18. A gate array comprising:

at least one diffusion strip; a plurality of gate electrodes formed above said diffusion strip and defining a plurality of MOS transistors within said diffusion strip; a plurality of gate array cells, each comprising a plurality of transistors, formed at least partially within said diffusion strip; and a plurality of isolation portions of said diffusion strip, said isolation portions being at the ends of said cells along the length of said diffusion strip, said isolation portions being coupled to a source of power, wherein adjacent ones of said cells share one of said plurality of isolation portions.

19. A gate array comprising: a core including a plurality of cells; a plurality of I/O cells having a first pitch; and a plurality of bonding pads having a second pitch which need not be equal to said first pitch, said bonding pads being programmable such that they are capable of being placed at any desired pitch without requiring the layout of said I/O cells to be altered.

20. A gate array comprising: a plurality of bonding pads, each having an associated width; and a plurality of I/O cells, each being associated with one of said bonding pads and having a width having a desired relation to said width of said associated bonding pad, each of said I/O cells comprising: one or more diffused strips having their lengths running generally perpendicular to said

width of said associated bonding pad; and one or more transistors formed within said diffused strips, having gate electrodes running generally perpendicualr to said length of said diffused strips.

21. A gate array as in claim 20 wherein said I/O cells include I/O buffer circuitry.

22. A gate array as in claim 20 wherein said I/O cells include a plurality of gates forming an I/O gate array.

23. A gate array as in claim 1 wherein the lowest one of said wiring layers comprises tungsten or an alloy thereof.

24. A gate array as in claim 23 which further comprises :

a substrate; a contact between said polycrystalline silicon layer and said substrate; a portion of a first wiring layer overlying said contact; a portion of a second wiring layer overlying said contact, said second wiring layer being separated from εaid first wiring layer by a layer of insulation; and a via formed within said layer of insulation providing electrical connection between said first wiring layer and said second wiring layer over said contact.

25. A gate array as in claim 1 which further comprises means for providing electrical interconnection between said layer of polycrystalline silicon and one or more of said vertical and/or horizontal wirings.

26. A method for personalization of a gate array cell to perform a desired electrical function comprising the steps of : defining the location for the subsequent formation of a diffusion strip; determining the number of transistors to be formed having source/drain regions located in said diffusion strip, based on said electrical function; determining which of εaid source/drain regions require a contact to provide electrical interconnection thereto in order to achieve said electrical function; forming polycrystalline silicon gate electrodes defining said transistors, adjacent ones of said gate electrodes being formed sufficiently spaced apart for the placement of a contact therebetween only if a contact is needed for electrical connection with a to- be-formed diffusion located therebetween; and forming said diffusion strip utilizing said gate electrodes as a mask, thereby forming said source/drain regions.