JPS6348122Y2 - - Google Patents

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Publication number
JPS6348122Y2
JPS6348122Y2 JP6648682U JP6648682U JPS6348122Y2 JP S6348122 Y2 JPS6348122 Y2 JP S6348122Y2 JP 6648682 U JP6648682 U JP 6648682U JP 6648682 U JP6648682 U JP 6648682U JP S6348122 Y2 JPS6348122 Y2 JP S6348122Y2
Authority
JP
Japan
Prior art keywords
wiring
circuit
bonding pads
region
pellet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP6648682U
Other languages
Japanese (ja)
Other versions
JPS58170833U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1982066486U priority Critical patent/JPS58170833U/en
Publication of JPS58170833U publication Critical patent/JPS58170833U/en
Application granted granted Critical
Publication of JPS6348122Y2 publication Critical patent/JPS6348122Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

Description

【考案の詳細な説明】 本考案は、モノリシツク集積回路（以下、IC
という）におけるペレツトのアルミ配線布線及び
リードフレームへのボンデイングに関するもので
ある。[Detailed explanation of the invention] This invention is a monolithic integrated circuit (hereinafter referred to as IC).
This paper relates to aluminum wiring of pellets and bonding to lead frames.

モノリシツクICの一般的な製造法に於いては、
ペレツト内に形成された多数の素子を接続する配
線領域は、アルミなどの低抵抗物質をペレツト全
面に形成した後、選択的に前記低抵抗物質を除去
することにより得られる。従つて、前記低抵抗物
質が一層構造の場合、原理的に配線の交差を行な
うことは不可能であるため、交差部直下に高濃度
拡散領域を形成し、交差する配線の一方を前記高
濃度拡散領域に接続し、もう一方の配線は絶縁層
を介して前記高濃度拡散領域の直上を通す方法が
よく用いられる。しかしながら、この方法では、
前記拡散領域はその外周の反対導電型半導体領域
に対して常に逆バイアス状態であることが必要で
あり、その部分に寄生容量が存在する。さらに、
前記高濃度拡散領域は、低抵抗物質に比べ、比較
的高抵抗を有する。 In the general manufacturing method of monolithic IC,
A wiring region connecting a large number of elements formed within a pellet is obtained by forming a low resistance material such as aluminum over the entire surface of the pellet and then selectively removing the low resistance material. Therefore, when the low-resistance material has a layered structure, it is theoretically impossible to cross the wiring lines, so a high concentration diffusion region is formed directly under the crossing point, and one of the crossing wiring lines is connected to the high concentration diffusion region. A method is often used in which the wiring is connected to the diffusion region and the other wiring is passed directly above the high concentration diffusion region via an insulating layer. However, with this method,
The diffusion region must always be in a reverse bias state with respect to the semiconductor region of the opposite conductivity type on its outer periphery, and a parasitic capacitance exists in that portion. moreover,
The high concentration diffusion region has a relatively high resistance compared to the low resistance material.

上記の理由から、上記高濃度拡散領域に接続さ
れる配線部の電位、およびその変化、付加される
容量成分と抵抗成分が回路の電気的特性に及ぼす
影響等を考慮しなければならず、時として交差さ
せることができないことがあり、そのため、配線
を長い距離にわたつて引き回したり、素子レイア
ウト配線設計の再考が必要となる。 For the above reasons, it is necessary to consider the potential of the wiring connected to the high-concentration diffusion region, its changes, and the effects of added capacitance and resistance components on the electrical characteristics of the circuit. Therefore, it is necessary to route the wiring over a long distance or to reconsider the element layout wiring design.

とりわけ、最近のICの高集積化およびペレツ
トサイズの大形化により、同一ペレツト内に多数
の回路ブロツクが形成されることが多くなり、各
ブロツク間に共通に使用される最高電位、最低電
位、およびその他の基準電位等の配線において
は、他の配線よりも比較的大電流が流れるにもか
かわらず、配線抵抗による電圧降下は各ブロツク
の特性に悪影響を与えるので、できる限り避けな
ければならない。従つて、この種の配線相互の交
差部に、前記高濃度拡散領域を用いた交差方法を
適用することは、抵抗成分の増加という点からも
好ましくなく、時としては、電位の関係から不可
能であることも少なくない。そのため、回路の電
気的特性を悪化させないためには、配線幅を太く
し、配線を引き回さなければならず、このことに
よるペレツトサイズの増大を余義なくされる。 In particular, with the recent increase in the integration density of ICs and the increase in pellet size, a large number of circuit blocks are often formed within the same pellet, and the highest potential, lowest potential, and Although relatively larger currents flow through other reference potential wiring than other wiring, voltage drops due to wiring resistance have an adverse effect on the characteristics of each block, and must be avoided as much as possible. Therefore, it is not preferable to apply the above-mentioned crossing method using a high concentration diffusion region to the intersection of this type of wiring because of the increase in the resistance component, and in some cases, it is impossible due to the potential relationship. There are many cases where this is the case. Therefore, in order not to deteriorate the electrical characteristics of the circuit, it is necessary to increase the wiring width and route the wiring, which inevitably increases the pellet size.

最近、上記のような問題が多くのICに見られ
るようになつたため、配線のための低抵抗物質の
形成を２層、もしくはそれ以上の多層構造にす
る、いわゆる多層配線技術の適用例が多く見うけ
られる。２層配線の構造は、第１図に示すように
なつている。すなわち、半導体領域１上には、第
１絶縁領域２が設けられ、第１絶縁領域２上に低
抵抗物質を形成後、選択的に除去することにより
第１配線領域３を得る。ここまでは一層だけの配
線形成工程と同一である。次に、第１配線領域３
の上に第２絶縁領域４を形成し、第２絶縁領域４
の一部を除去し、下部の第１絶縁領域３に達する
ようなスルーホール部を形成した後、第２配線領
域５を形成し、第１配線領域と同様、選択的に低
抵抗物質を除去することにより、所望の配線を実
現できる。 Recently, the above-mentioned problems have been seen in many ICs, so there are many applications of so-called multilayer wiring technology, which forms low-resistance materials for wiring into a two-layer or more multilayer structure. You can see it. The structure of the two-layer wiring is as shown in FIG. That is, a first insulating region 2 is provided on the semiconductor region 1, and a first wiring region 3 is obtained by forming a low-resistance material on the first insulating region 2 and then selectively removing it. The process up to this point is the same as the wiring formation process for only one layer. Next, the first wiring area 3
a second insulating region 4 is formed on the second insulating region 4;
After forming a through-hole portion that reaches the first insulating region 3 at the bottom, a second wiring region 5 is formed, and similarly to the first wiring region, the low-resistance material is selectively removed. By doing so, desired wiring can be realized.

このような構造を用いることにより、配線の交
差は自由に行なうことが可能で、交差部の抵抗分
増加もほとんどなく、回路の電気的特性に影響を
与えることが少ない夫線設計を容易に行なえる。 By using such a structure, wiring can be freely crossed, there is almost no increase in resistance at the intersection, and it is easy to design a husband wire that has little effect on the electrical characteristics of the circuit. Ru.

しかしながら、多層配線構造は、その形成のた
めには、通常の一層配線に比べて少なくとも各１
回ずつ、絶縁領域形成、スルーホール部形成、上
部配線領域形成という付加工程が各層形成ごとに
必要となる。このような付加工程の追加は、IC
の歩留り低下を招くことと相まつて、ICの製造
コストの上昇の原因となり、さらに各配線領域間
の容量結合が回路に影響をおよぼす場合があると
いう欠点があつた。 However, in order to form a multilayer wiring structure, it is difficult to form a multilayer wiring structure.
Additional steps of forming an insulating region, forming a through-hole portion, and forming an upper wiring region are required for each layer formation. The addition of such additional processes is
In addition to causing a decrease in yield, this also causes an increase in the manufacturing cost of the IC, and has the disadvantage that capacitive coupling between each wiring area may affect the circuit.

本考案の目的は、配線の交差部における抵抗成
分、配線の引き回しによる布線抵抗成分の増大
を、多層配線技術を用いることなく、従来工程の
みで軽減させることを可能にした半導体集積回路
を提供することである。 The purpose of the present invention is to provide a semiconductor integrated circuit that makes it possible to reduce the resistance component at the intersection of wires and the increase in wiring resistance component due to the routing of wires using only conventional processes without using multilayer wiring technology. It is to be.

以下、図面をもとに本考案を説明する。 The present invention will be explained below based on the drawings.

第２図は、本考案の説明のために示したICの
ブロツク回路図である。この回路は、ステレオ電
力増幅回路を示したものであり、右側、左側両チ
ヤンネルにそれぞれ独立した入出力端子を有する
電力増幅回路を有し、かつ共通の電源端子、およ
び接地端子をIC外部に取り出している。第２図
において６ａ，６ｂはおのおの電力増幅回路、７
ａ，７ｂは出力端子、８ａ，８ｂは入力端子、９
は電源端子（最高電位）、１０は接地端子（最低
電位）である。ステレオ回路においては、両チヤ
ンネルの増幅回路の特性が同一で、かつ、両チヤ
ンネル相互が干渉しないことが重要な特性であ
り、第２図の回路をIC化するさい、布線設計を
正しく行なわないと、両チヤンネルの電源端子、
接地端子への布線インピーダンスの差による特性
の誤差を生じたり片チヤンネルに大電流が流れる
ことによつて、共通である電源端子および接地端
子に接続された配線部の電圧降下を生じ、実効的
にもう一方のチヤンネルの電源電圧を降下させ、
増幅回路の入出力特性が変化することになる。 FIG. 2 is a block circuit diagram of an IC shown for explaining the present invention. This circuit shows a stereo power amplifier circuit, which has a power amplifier circuit with independent input and output terminals for both the right and left channels, and the common power supply terminal and ground terminal are taken out to the outside of the IC. ing. In FIG. 2, 6a and 6b are respective power amplifier circuits, and 7
a, 7b are output terminals, 8a, 8b are input terminals, 9
is a power supply terminal (highest potential), and 10 is a ground terminal (lowest potential). In a stereo circuit, it is important that the characteristics of the amplifier circuits of both channels are the same and that the two channels do not interfere with each other.When converting the circuit shown in Figure 2 into an IC, it is important that the wiring design is not done correctly. and power terminals for both channels,
Errors in characteristics due to differences in wiring impedance to the ground terminal or large current flowing in one channel may cause a voltage drop in the wiring connected to the common power supply terminal and ground terminal, resulting in an effective to lower the power supply voltage of the other channel,
The input/output characteristics of the amplifier circuit will change.

第３図は、第２図の回路を従来の布線設計に従
つてIC化し、リードフレームに実装し、ワイヤ
リードを結線した状態を示したものである。第３
図に於いて、１１，１２，１３，１４，１５，１
６はそれぞれICペレツト上の配線領域内に設け
られたリード線を接続するためのボンデイングパ
ツド、１７はペレツトを示す。第３図に於いて
は、特に接地端子１０に接続されるボンデイング
パツド１６から両チヤンネル回路への配線部分
が、片チヤンネルは長く引き回されており、大電
流が流れた際、両チヤンネルの布線インピーダン
スによる電圧降下に差を生じ、両チヤンネルの特
性が異なることが懸念される。ボンデイングパツ
ド１１，１２…，１６の位置は、IC外部に引き
出されるリードフレーム端子の位置によつて制限
され、リードフレーム端子７ａ，７ｂ，８ａ，８
ｂ，９，１０の位置、すなわちICのピン配置は、
回路特性よりはむしろIC実装上の要因により決
定されるのが常であり、容易に布線を変更するこ
とは不可能である。 FIG. 3 shows the circuit of FIG. 2 converted into an IC according to the conventional wiring design, mounted on a lead frame, and connected with wire leads. Third
In the figure, 11, 12, 13, 14, 15, 1
6 denotes bonding pads for connecting lead wires provided in the wiring area on the IC pellet, and 17 denotes a pellet. In Figure 3, in particular, the wiring from the bonding pad 16 connected to the ground terminal 10 to both channel circuits is routed long on one channel, so that when a large current flows, both channels There is a concern that there will be a difference in voltage drop due to wiring impedance, and that the characteristics of both channels will be different. The positions of the bonding pads 11, 12, . . . , 16 are limited by the positions of the lead frame terminals drawn out to the outside of the IC.
The positions of b, 9, and 10, that is, the pin arrangement of the IC, are
It is usually determined by IC mounting factors rather than circuit characteristics, and it is impossible to easily change the wiring.

これに対し、第４図は、第２図と同一の回路を
第３図に示したものと同一のリードフレームを用
い、本考案を適用して布線設計を行ない、ボンデ
ングワイヤを接続した一実施例を示したものであ
る。図において、１１ａ，１１ｂは第３図に於い
ては１個であつたボンデイングパツド１１を２個
に変更して電源端子９に接続されるボンデイング
パツドである。 On the other hand, Fig. 4 shows the same circuit as Fig. 2 using the same lead frame as shown in Fig. 3, applying the present invention to the wiring design, and connecting bonding wires. This shows an example. In the figure, reference numerals 11a and 11b designate bonding pads 11 which are connected to the power supply terminal 9, with the bonding pad 11 having been changed from one in FIG. 3 to two.

このような構造とすることにより、第３図に於
いて長く引き回されていた電力増幅回路６ｂへの
接地配線は、電源端子へ接続されるボンデイング
パツド１１ａ，１１ｂの間を通つて接地端子１０
へのボンデイングパツド１６へと接続されてい
る。従つて、両チヤンネルの電力増幅回路から電
源端子９及び接地端子１０までの配線がほぼ等距
離とすることができ、第３図の場合懸念された両
チヤンネルの特性の差が生じることは解消された
ことになる。さらに、ペレツト外周に沿つて引き
回していた配線を不必要にしたことによりペレツ
トサイズの縮小化もはかることができる。 With this structure, the ground wiring to the power amplifier circuit 6b, which had been routed for a long time in FIG. 10
to the bonding pad 16. Therefore, the wiring from the power amplifier circuits of both channels to the power supply terminal 9 and the ground terminal 10 can be made at approximately the same distance, and the difference in characteristics between the two channels, which was a concern in the case of FIG. 3, is eliminated. That means that. Furthermore, the pellet size can be reduced by eliminating the need for wiring that was routed along the outer periphery of the pellet.

以上の一実施例に示したように、本考案は、同
一の電位が供給される導電体領域を複数個の領域
に分割し、それぞれの領域にはボンデイングパツ
ドが近接配置されて設けられ、かつ前記複数個の
ボンデイングパツドは同一の外部リードフレーム
端子に接続されるとともに、前記近接配置の複数
個のボンデイングパツド間を通して他の電位を供
給する導電体配線が設けられたところの半導体装
置を与えるものである。 As shown in the above embodiment, the present invention divides a conductive region to which the same potential is supplied into a plurality of regions, and each region is provided with bonding pads arranged close to each other. and a semiconductor device, wherein the plurality of bonding pads are connected to the same external lead frame terminal, and a conductor wiring is provided for supplying another potential through the plurality of bonding pads arranged in close proximity to each other. It gives

本実施例では、最高電位である電源端子への配
線と最低電位である接地端子への配線について適
用した場合を述べたものであるが、その他の配線
領域において適用してもなんらさしつかえない。 Although this embodiment describes a case in which the present invention is applied to wiring to a power terminal having the highest potential and wiring to a ground terminal having the lowest potential, there is no problem in applying the present invention to other wiring areas.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は一般的な２層配線構造を示すICの部
分断面図、第２図は本考案を設明するためのIC
内部のステレオ用２チヤンネル電力増幅回路のブ
ロツク図、第３図は第２図の回路をIC化したペ
レツトおよびリードフレームへの結線状態の一例
を示した上面図、第４図は本考案の一実施例にお
けるIC化したペレツトおよびリードフレームへ
の結線状態を示した上面図である。 ６ａ，６ｂ…電力増幅回路、７ａ，７ｂ，８
ａ，８ｂ，９，１０…リードフレーム端子、１１
ａ，１１ｂ…近接配置のボンデイングパツド、１
２，１３，１４，１５，１６…導電体領域毎のボ
ンデイングパツド、１７…半導体ペレツト。 Figure 1 is a partial cross-sectional view of an IC showing a general two-layer wiring structure, and Figure 2 is an IC for establishing the present invention.
A block diagram of the internal stereo 2-channel power amplifier circuit, Fig. 3 is a top view showing an example of the connection state to the pellet and lead frame, which is an IC version of the circuit in Fig. 2, and Fig. 4 is one example of the circuit of the present invention. FIG. 2 is a top view showing a pellet formed into an IC and a state of connection to a lead frame in an example. 6a, 6b...power amplifier circuit, 7a, 7b, 8
a, 8b, 9, 10...Lead frame terminal, 11
a, 11b...bonding pads arranged in close proximity, 1
2, 13, 14, 15, 16... Bonding pads for each conductor region, 17... Semiconductor pellet.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 一つの半導体ペレツト内の同一電位が供給され
る複数個の導電体領域にそれぞれ独立のボンデン
グパツドを有し、前記複数個のボンデイングパツ
ドは互いに近接配置されて同一の外部リードフレ
ーム端子へ接続され、かつ、前記近接配置のボン
デイングパツドの間を通つて、他の電位を供給す
る導電体領域が設けられていることを特徴とする
半導体集積回路。 A plurality of conductive regions within one semiconductor pellet to which the same potential is supplied each have independent bonding pads, and the plurality of bonding pads are arranged close to each other and connected to the same external lead frame terminal, A semiconductor integrated circuit further comprising: a conductor region for supplying another potential through between the bonding pads arranged close to each other.
JP1982066486U 1982-05-07 1982-05-07 semiconductor integrated circuit Granted JPS58170833U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982066486U JPS58170833U (en) 1982-05-07 1982-05-07 semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982066486U JPS58170833U (en) 1982-05-07 1982-05-07 semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS58170833U JPS58170833U (en) 1983-11-15
JPS6348122Y2 true JPS6348122Y2 (en) 1988-12-12

Family

ID=30076354

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982066486U Granted JPS58170833U (en) 1982-05-07 1982-05-07 semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS58170833U (en)

Also Published As

Publication number Publication date
JPS58170833U (en) 1983-11-15

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