JPH0815258B2 - Programmable CMOS logic array - Google Patents

Description

The present invention relates to a programmable CMOS logic array, and more particularly to a programmable CM suitable for a CMOS gate array.
Regarding OS logic array.

[Conventional technology]

Conventionally, CMOS status logic arrays (hereinafter referred to as PLA) have been used as IEE, Journal of Solid State Circuits, ESC.
11, Number 3 (1976) Pages 365 to 369 (IEEE,
Journal of Solid-State Circuits, SC-11 (1976) pp365
-369). Here, in order to reduce the size, both the AND and OR matrixes are configured by using a load MOS as a PMOS and a driver MOS corresponding to an input signal line as an NMOS. Also, as in the case of a normal PLA, the AND matrix and the OR matrix are laid out as separate blocks. However, in this conventional layout method, since the logic specification is programmed by changing the gate oxide film thickness under the polysilicon (Poly-Si) layer, if the logic specification is changed and the design is changed, the underlying process step is changed. , The design change was not easy, and no consideration was given to the ease of design change.

As described above, conventionally, the design development time was shortened, the change was facilitated, and the consideration of the gate utilization rate was insufficient. In the case of a gate array, the third point of the gate utilization rate among these three elements is that a plurality of pairs of PMOS and NMOS are used as basic cells and the basic cells are regularly arranged on the chip as a base. Especially important.

On the other hand, in order to overcome the above problems, Japanese Patent Publication No. 60-57732
No. 60-57733 is published. In these examples, improvements are made to a regular CMOS NAND gate. That is, these are the PMs in the conventional multi-input NAND gate.
OS can be connected to positive input signal and inverted input signal respectively 2
Each PMOS pair is formed by replacing each NMOS with two NMOS pairs in which a positive input signal and an inverted input signal can be connected.

In this case, it has a static and low power consumption characteristic, but the number of MOS transistors is usually twice that of the gate,
If the logic scale is not significantly large, there is a possibility that the area efficiency will be significantly reduced as compared with the case where it is configured with a normal gate. Further, as the number of input signal lines increases, the number of NMOSs connected in series between the ground power supply and the output point increases, so that the output delay delay increases and the input logic threshold voltage V _LT increases. The design of the output driver in the next stage tends to be difficult. Therefore, the number of input signal lines is usually restricted.

 Here, the gate array will be described.

The gate array is for manufacturing an LSI having a desired electric circuit operation by creating only a mask corresponding to wiring out of a dozen or more masks used when manufacturing an LSI according to the development type.

The structure of a conventional gate array LSI is shown in FIG. The LSI chip 1 has a bonding pad and an input / output circuit area 5 on the outer periphery thereof, and a basic cell row 3 in which basic cells 2 composed of elements such as transistors are arranged in the X-axis direction and a wiring area 4 are sandwiched inside. It adopts a configuration that is repeatedly arranged in.
Adjacent basic cells 2 to obtain the desired electric circuit operation
One or several wires are connected to form a NAND gate or flip-flop. Then, various logic gates formed by a plurality of basic cells 2 are connected according to a logic diagram to form one LSI.

FIG. 3 shows a plan view of the basic cell 2 as an example. The basic cell 2 is formed in an N-type substrate to form a p + type region 6 serving as a source or drain of a P-type MOS transistor, an N + type region 7 serving as a source or a drain of an N type MOS transistor, and an N + type region 7. P-WELL area 12, p and two poly-Si gate electrodes 8 shared by N-type MOS transistors, Vcc power line 10 and GND for supplying power to both transistors
A contact hole 9 for connecting the power supply line 11, p +, N + diffusion layers 6 and 7 serving as a source or a drain and an Al wiring (not shown) and a contact hole 9 for connecting a gate electrode 8 and the Al wiring. ’

As another example of the basic cell, a 4-input type plan view is shown in FIG. The same or like parts as those in the above drawings are designated by the same reference numerals. Since the structure is almost the same as that of FIG. 3, the description of the structure is omitted. The difference is that the source or drain region is composed of four series of PMOS and NMOS formed by the same diffusion layer. Therefore, by applying a wiring process to this, one 4-input gate can be formed. The fourth
In the figure, the poly-Si gate electrode 8 is indicated by a solid line, and the position 9'where the contact hole on the gate electrode can be formed is indicated by a circle. Reference numeral 13 indicates the position of the contact hole for applying the substrate bias, 14 indicates the position of the contact hole for applying the p-WELL bias, and the lattice point indicates the wiring channel for the in-cell wiring (matches the DA lattice line on the wiring area).

The plan view of FIG. 4 can be represented as shown in FIG. 5 using MOS symbols. Hereinafter, the wiring pattern will be shown on the top of this figure for simplification of the drawing.

FIG. 2 shows a conventional fixed channel type gate array, but in recent years, a fully spread type gate array having a different architecture from this has been attracting attention. For this, see I.E.E.Proceeding of Custom Integrated Circuit Conference Conference (May 20-23, 1985), pages 15 to 17 (Proceedings of IEEE 1985 Custom Integrated Circu).
its Conterence). The full-faced type is a type in which basic cells are arranged on the entire surface of the chip internal region, and the characteristics of the variable channel region are maximized to increase the number of mounted gates. This will be described with reference to the master chip configuration shown in FIG. In a peripheral area 51 on the chip 50, an external cell 52 including an input / output buffer and a bonding pad (not shown) are arranged. Basic cells 53 are laid all over the inner area 54. Therefore, the wiring channel can be selected in the unit of height of the basic cell, or by making the basic cell symmetrical as described in the above-mentioned document, in the unit of height of half the basic cell. Therefore, high-density mounting is possible.

In addition, a large macro cell can be mounted at a significantly higher density than the conventional fixed channel method, so that the effect is great. In FIG. 6, in addition to the macro cells of ROM, RAM and PLA, ALU and analog super macros are also shown. In the all-overlaid type, the macrocells can be freely arranged and the capacity is variable, so that they have versatility suitable for a gate array.

The present invention provides a programmable CMOS logic array which is particularly suitable for this all-overlaid gate array.

[Problems trying to solve the invention]

The above-mentioned conventional technology is easy to design change, versatile,
No consideration was given to downsizing, and there was an inappropriate problem especially when a CMOS cell structure such as a gate array was adopted.

The object of the present invention is to make it possible to reduce the size by matching with a cell of CMOS structure such as a gate array, and according to the capacity specified by the user.
It is to provide a programmable CMOS logic array that can be easily expanded to a macro cell by DA (Design Antomation).

[Means for solving problems]

According to the present invention, in a horizontal PLA circuit, an AND matrix is connected in parallel between each output signal line and one power supply line.
It consists of a PMOS (or NMOS) and a load MOS connected between the output signal line and the other power supply line, and OR matrix is connected in parallel between each output signal line and the other power supply line. Each of n NMOSs (or PMOSs) and a load MOS connected between the output signal line and one power supply line.
The input signal lines corresponding to the gate electrodes of the S and NMOS are separated and arranged, and the two are connected by a wiring layer mask to perform a logic program.

The number of input signal lines n and the number of term lines 1 showing the principle of the present invention
FIG. 1 shows a PLA circuit having one output signal line and m output signal lines. This PLA circuit is composed of an AND matrix 100 and an OR matrix 101. The AND matrix 100 includes inverters DR _{0 to} DR _n-1 and load NMOS NL _{0 to} N.
L _l-1, is constituted by One Manzanillo and output drivers BF ₀ ~BF _l-1 and n × l number of PMOS. On the other hand, OR Matrix 101
Load PMOS PL _{0 to} PL _n-1 , output drivers OB to OB _m-1 , and l
It is composed of × m NMOSs. As is apparent from the above configuration, in the present invention, the number of PMOS (NMOS) is 1 per input and 1 term, and the number of NMOS (PMOS) is 1 term,
Since one output is sufficient for one output, the number of MOSs can be reduced by half compared to the conventional CMOS static type.

In this configuration, since many PMOSes or NMOSs are connected between the output point and the power supply line, it is necessary to design the load MOS in consideration of the ratio. In the gate array, since the MOS size is uniform, this ratio design is performed by connecting many MOSs in series. In FIG. 1, one MOSDE is shown for convenience. Also, by controlling the resistance of the load MOS, it is possible to make a trade-off between power consumption and operating speed.

[Action]

Next, the operation of the present invention will be described. First, in the AND array, the same output signal line is assigned to each input signal line I _{0 to} I _n-1.
N PMOSs connected to the Vcc power source electrode are connected to T _j ′. The gate electrode 8 of each PMOS is separated from the input signal line, and a desired I _i or ▲ can be obtained by forming a contact hole at the position 9 '(indicated by X in FIG. 1). Connected with ▼. T _i ′ is the input signal I ₀ ~
NAND logic output for I _n-1 ( _{0 to} I _n-1 ) and T _i for AND logic output. In the case of FIG. 1, the following logical expression is programmed.

Next, in the OR array 101, l NMOSs whose source electrodes are connected to the GND power source are connected to the same output signal line O _i ′ corresponding to each term line T _{0 to} T _l−1 . Also in this case, similarly to the above, the gate electrode of each NMOS is connected to a desired term line T _i by forming a contact hole at a position 9 '.
O _i ′ has a NOR gate function for the input signals (term signals) T _{0 to} T _l−1 . When viewed from the output signal lines of the output drivers OB _{i to} OB _n-1 , the whole becomes an OR array.

As described above, according to the present invention, the gate electrode I
It can be changed by connecting to _i ( _i ), that is, only by the wiring pattern. Further, according to the present invention, if there is no difference between the number of input signals and the number of output signals, the PMOS used
The number of NMOSs and the number of NMOSs may be almost the same, and when the basic cells are used like a gate array, the mounting rate can be improved.

Furthermore, according to the present invention, a unit PLA cell in which an AND matrix and an OR matrix are integrated is possible, which has an effect of improving the packaging density and facilitating the macro cell expansion by DA.

〔Example〕

 Examples of the present invention will be described below.

 FIG. 7 shows an embodiment of the present invention.

In this embodiment, a PLA macrocell according to the present invention is constructed in a full-gate-laid gate array in which the basic cells shown in FIGS. In FIG. 7, 53 indicated by a chain line is four PMs.
A basic cell consisting of a pair of OS and NMCS, which are arranged side by side in the X-axis and Y-axis directions. A logic cell or a macro cell composed of a wiring pattern is arranged on this base to obtain a desired electric circuit operation. The wiring pattern in the block 53, that is, the logic cell is an AND / OR integrated unit cell (2 inputs, 2 terms, 2 outputs), 2
03 is a block constituting the output drivers OB _{0 to} OB _m-1 , 201
Is a block constituting the output drivers BF _{0 to} BF _l-1 , 202 is a load NMOS consisting of two series-connected NMOSs, and NL _{0 to} NL _l-1 is a block, and 204 is an l / 2 in the X-axis direction. N / n in the Y-axis direction
PL consisting of 2 or m / 2 integrated unit cells arranged in parallel
This is A matrix block. The solid line in the wiring pattern shown in FIG. 7 is the first layer aluminum (A1),
The broken line is the second layer aluminum (Al2), the X mark is the contact hole for connecting the diffusion layer or poly-Si and A1, and the O mark is A.
This is a contact hole formed in the interlayer insulating film for connecting 1 and Al2. In order to connect the diffusion layer or poly-Si to Al2, first, the contact holes x and ◯ are formed in the corresponding places, and both are connected by A1.

Of the four PMOSs in the basic cell 53, two PMOSs each have a source and a drain connected between the Vcc power supply and the output signal lines T ₀ ′ and T ₁ ′. That is, the drains of the two PMOSs on the left are
To the T ₀ ′ side, the drains of the two PMOSs on the right side are connected to the T ₁ ′ side. The T ₀ ′ signal line and the T ₁ ′ signal line are wired in the Y-axis direction with Al2, and are connected to the gate electrode of the block 201 of the output driver arranged on the extension thereof. The output driver comprises a parallel connection structure of two PMOSs and a parallel connection structure of two NMOSs to form a power driver. Therefore, one basic cell can form two power drivers,
The pitches of T ₀ ′, T ₁ , T ₂ ′, T ₃ ′ and the array peach of the power driver can be matched. At the same time, T ₀ ′ and T ₁ ′ are input to the load NMOS block 202 and pulled down by two NMOSs connected in series whose gate electrodes are fixed to the Vcc power supply. Also in this case, the pitches of T ₀ ′ and T ₁ ′ and the arrangement pitch of the load NMOS cells can be matched.

On the other hand, the output signal line O _i ′ of the OR matrix connects the common drains of the two NMOSs whose sources are connected to the GND potential line among the four NMOSs in the same basic cell in common through the contact hole ×. Then, the NMOSs in the same basic cell are wired in the X-axis direction. That is, the output signal lines O ₀ ′, O ₁ ′,
O ₂ ′, O ₃ ′ ... constitute the NOR gate output. However, the pull-up MOS cell connected to the output signal line O _i ′ is not shown. Since the output signal lines O ₀ , O ₁ , O ₂ , O ₃ , ... Are passed through the output driver cell 203, they are OR logic outputs with respect to the term inputs T ₀ , T ₁ , T ₂ , T ₃ . .

The logic program is performed as follows. First, AND
The matrix will be described. However, of the two PM6S connected in series to the same output signal line T _i ′, the left PMOS is for the input signal lines I _j , _j , and the right PMOS is for the input signal lines I _{j + 1} ,
_Suppose it is for _{j + 1} . The logic program is performed by connecting a predetermined input signal line to the gate electrode of the PMOS. This connection pattern is formed by the X-shaped contact hole and the A1 wiring layer.

The connection pattern described above is shown by the thick solid line and the contact hole in FIG. In the above program, the MOS that does not take logic has the gate electrode Vcc or GND.
Although it is necessary to fix it at the electric potential, these connection patterns are omitted in FIG. 7 for simplification. The various connection patterns described above are prepared as, for example, several types of cells (called modi-eye cells) for one basic cell,
It can be placed on a matrix according to the logic program specifications, and has the feature that the automatic expansion and generation of PLA macrocells by DA is easy.

The operation is the same as that shown in FIG. 1, and therefore its explanation is omitted.

FIG. 8 is a block diagram showing the embodiment of FIG. PLA macrocell is a block of input buffer 2
10, AND / OR integrated unit cell 53, output driver block
A load MOS block 202 for AND matrix 202, a block 203 for output driver, and a load MOS block 211 for OR matrix. Numerical values and symbols in the figure represent the number in the X-axis direction and the number in the Y-axis direction (the number of steps) in units of basic cells. Therefore, if the number of input signals is n, the number of terms is 1, and the number of output signal lines is m, the size of the PLA macrocell is (l / 2 + 3) × n / 2, or (l / 2 + 3).
× m / 2. The cell structure of the unit cell 53 is shown in FIG. This shows the relationship of the input / output signals of 53 in FIG. 7, and the input signal lines I _i-1 , I in the unit cell are A1.
_i , _i , and the output signal lines O _i-1 , O _i run in the X-axis direction, and the term lines T _j-1 , T _j run with Al2 in the Y-axis direction.

In this way, in this embodiment, the control wiring passes over the MOS transistor, so that the packaging density can be increased.

FIG. 10 shows another embodiment and shows an AND matrix circuit. However, only the AND logic part of the term T _i is shown. This AND logic unit includes PMOS P ₀ , P ₁ ... P _n-1 , output driver B
It consists of Fi and NMOS NL ₀₀ , NL ₀₁ , NL ₀₂ , and NL ₀₃ that compose the load NMOS. In this embodiment, the load MOS is improved, and other configurations and operations are the same as those in the above-mentioned embodiments, and therefore the description thereof will be omitted.

In the load MOS according to this embodiment, the gate electrode is the output signal line T
_The source and drain are connected in series to each other and connected to _i ', and are composed of four NMOSs. The "1" level voltage VOH of the output signal line T _i ′ becomes about 2 to 3 V depending on the ratio between the PMOS and the load NMOS. Therefore, the voltage level of the gate electrode of the NMOS is 2
The resistance of the NMOS is increased by holding down to 3 V, and the direct current consumption can be reduced.

〔The invention's effect〕

According to the present invention, the AND matrix and the OR matrix can be formed by complementary MOSs, and a layout configuration in which the both matrices are integrated is possible, so that a PLA using a cell having a CMOS structure can be formed in a small size and DA (Design
Automation) makes it easy to generate PLA macrocells. In particular, it has a great effect when forming a PLA macrocell with a gate array of full-scale gates.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing the principle of the present invention, FIG. 2 is a chip plan view showing a conventional example, FIGS. 3 and 4 are plan views showing basic cell examples, and FIG. 5 is a pattern diagram of basic cells. FIG. 6 is a chip plan view of a full-face gate spread type date array, FIG. 7 is a connection diagram showing an embodiment of the present invention, FIG. 8 is a block diagram supplementing FIG. 7, and FIG. A block diagram supplementing FIG. 8 and FIG. 10 are circuit diagrams showing another embodiment. 100 …… AND matrix, 101 …… OR matrix, 20
1,203 …… Output driver block, 202 …… Load MOS block.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/112

Claims (4)

[Claims] 1. Each of n positive input signal lines and inverting input signal lines, one or more output signal lines, and n PMOSs connected in parallel between a power source line and each of the output signal lines. Or NMOS) transistor, and comprising a resistance element or load MOS transistor connected between each output signal line and the ground, for the pair of the positive input signal line and the inverted input signal line,
Each one of the PMOS (or NMOS) transistors is provided,
The positive input signal line and the inverted input signal line corresponding to the gate electrode of the PMOS (or NMOS) transistor are arranged in an open state, and if necessary, the positive input signal line or the inverted input signal line of the positive input signal line or the inverted input signal line is masked with a wiring layer mask. Programmable CM characterized by connecting to any of them to perform a logic program
OS logic array. 2. The device according to claim 1, wherein at least two PMOS transistors in which sources or drains are connected in series and at least two NMOS transistors in which sources or drains are connected in series are arranged relative to each other. A logic gate macrocell is formed by using a CMOS gate array in which the following basic cells are regularly arranged on a chip, and a PMOS transistor is an AND array, an NMOS transistor is an OR array, or a PMOS transistor in the basic cell. Is a programmable CMOS logic array characterized in that it is formed by using an OR array and an NMOS transistor as an AND array. 3. An AND array and an OR array are connected in parallel between each of n positive input signal lines and inverting input signal lines, one or more output signal lines, and a power supply line and each of the output signal lines. A pair of the positive input signal line and the inverting input signal line, the n-type PMOS (or NMOS) transistor and the resistance element or the load MOS transistor connected between each output signal line and the ground. For each one of the PMOS (or
An NMOS transistor is provided, and the positive input signal line and the inverted input signal line corresponding to the gate electrode of the PMOS (or NMOS) transistor are arranged in an open state, and the positive input signal line is masked with a wiring layer mask if necessary. Alternatively, the AND array is configured to be connected to any one of the inverted input signal lines, and the AND array is formed by (the number of input signal lines n) × (the number of output signal lines) PMOS (or NMOS) transistors and the number of the output signal lines of the resistors. Element or load MOS transistor, OR array (number of input signal lines n) × (number of output signal lines) NMOS (or PMOS)
Transistor and resistance element or load with several output lines
Programmable CMOS logic array characterized by being formed by MOS transistors. 4. The device according to claim 3, wherein at least two PMOS transistors having sources or drains connected in series and at least two NMOS transistors having sources or drains connected in series are arranged relative to each other. A logic array macrocell is formed using a CMOS gate array formed by regularly arranging basic cells formed on a chip, and PMOS transistors are AND arrays and NMOS transistors are OR arrays in the basic cells.
Alternatively, a programmable CMOS logic array in which PMOS transistors are formed to be used as an OR array and NMOS transistors are used as an AND array.