JPS62263652A - Programmable cmos logic array - Google Patents

Abstract

PURPOSE:To miniaturize a CMOS static logic array using a cell having CMOS structure by mutually forming an AND matrix and an OR matrix by complementary MOSs and shaping layout constitution in which both matrices are unified. CONSTITUTION:An AND matrix 100 is organized of inverters DR0-DRn-1, load NMOSs NL0-NLl-1, output drivers BF0-BFl-1 and nxl PMOSs. On the other hand, an OR matrix 101 is constructed of load PMOSs PL0-PLn-1, output drivers OB-OBm-1l and lxm NMOSs. One may he used regarding one input and one term as the number of the PMOSs (NMOSs) and one regarding one term and one output as the number of NMOSs (PMOSs), thus reducing the number of the MOSs by half. Since a large number of the PMOSs or NMOSs are connected between an output point and a power line, the load MOSs must be designed in consideration of a ratio. Since MOS size is equalized in a gate array, a design considering the ratio is conducted by connecting a large number of the MOSs in series.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a programmable CMOS logic array, and particularly to a programmable CMOS logic array suitable for a CMOS gate array.

[Conventional technology]

Conventionally, CM OS static logic array (hereinafter referred to as P
Regarding L.A.), I.E.E.E.
Journal of Solid State Circuits, Varnish Sea 11. Number 3 (1976), pp. 365-369 (IEEE.

Journal of 5solid-5tate C1
rcu, Lts, SC-11 (1976) pp36
5-369). There, we use AND for miniaturization.

For both OR matrix, load MO8 is PMOS.

The driver MO8 corresponding to the input signal line is composed of NMOS. Also, like a normal PLA, an AND matrix and an OR matrix are laid out as separate blocks. However, in this conventional layout method, the logic specifications are programmed by changing the thickness of the gate oxide film under the polysilicon (Poly-S i ) layer, so if the logic specifications are changed and the design is changed, the underlying process steps must be changed. Therefore, it was not easy to change the vU meter, and no consideration was given to the ease of design changes.

As described above, in the past, consideration has not been given to shortening the design development time, facilitating changes, and gate utilization rate. This 3
In the case of a gate array, the third point of gate utilization among the two elements is multiple PMOS.

Since the NMO3 pairs are used as basic cells and the basic cells are arranged regularly on the chip as a base, it is particularly effective.

On the other hand, in order to overcome the above problems,
No. 732 and Special Publication No. 60-57733 have been published.

In these examples, improvements are made to the usual CMO3N'AND gate. In other words, these are the conventional durability N
In the AND game i-, each PMOS is connected to two PMOS pairs to which positive input signals and two inverted input signals can be connected, and each NMOS is connected to two pairs to which positive input signals and two inverted input signals can be connected. It is replaced with NMOS pairs and formed in an array.

In this case, it is static and has the characteristic of low power consumption,
! The number of viO8 transistors is twice as large as that of a normal gate, and unless the logic scale is considerably large, there is a risk that the area efficiency will be significantly lower than when configured with normal gates. Furthermore, as the number of input signal lines increases, the number of NMO3s connected in series between the ground power source and the output point increases, which tends to make it difficult to measure the fall replay of the output. Therefore, the number of input signal lines is usually limited.

Here, the gate array will be explained.

A gate array is an LSI that has the desired electrical circuit operation by creating only the mask corresponding to layout a out of the ten or so masks used when manufacturing LSI according to the developed product.
It manufactures.

The configuration of a conventional gate array LSI is shown in Figure 2.
The I-chip 1 has a bonding pad and an input/output circuit area 5 on its outer periphery, and has inside a basic cell row 3 in which basic cells 2 made up of elements such as transistors are arranged in the X-axis direction.
A configuration is adopted in which these are repeatedly arranged across the wiring area 4. In order to obtain a desired electrical circuit operation, one or several adjacent basic cells 2 are connected to form a NAND gate, a flip-flop, or the like. Then, one LSI is formed by connecting various logic gates formed by a plurality of basic cells 2 according to a logic diagram.

FIG. 3 shows a plan view of the basic cell 2 as an example.

The basic cell 2 includes a P-shaped region 6. which becomes the source or drain of a P-type MOS transistor. N-type region 7, which becomes the source or drain of the N-type MoS transistor. N
p formed in the N-type substrate to form a decagonal region 7
- WELL region 12°p and two poly-Si gate electrodes 89 shared by the N-type MOS transistor; Vcc power line 10 for supplying power to both transistors; GND power supply fil
A contact hole 1 for connecting the p+, N+ diffusion layer 6°7 and the AQ wiring (not shown) and the gate electrode 8 to connect the AQ wiring (not shown) to the AQ wiring (not shown). The contact hole 9' is made up of a contact hole 9'.

FIG. 4 shows a plan view of a four-person type cell as another example of the basic cell. Equivalents and identical parts to those in the previous drawings are designated by the same reference numerals. Since most of the configuration is the same as that shown in FIG. 3, a description of the configuration will be omitted. The difference is that the source or drain region consists of four series of PMO3 and NMOS formed by the same diffusion layer. Therefore, by performing a wiring process on this, one four-person gate can be formed. In FIG. 4, the poly-Si gate electrode 8 is indicated by a solid line, the position 9' where a contact hole can be formed on the gate electrode is indicated by a circle, 613 is the contact hole position for applying a substrate bias, and 14 is the position for applying a p-WELL bias. Indicates the contact hole position,
The grid points indicate wiring channels for intra-cell wiring (coinciding with DA grid lines on the wiring area).

The plan view of FIG. 4 can be represented using MOS symbols as shown in FIG. 5. Hereinafter, in order to simplify the drawing, the wiring pattern will be shown on the top of this figure.

FIG. 2 shows a conventional fixed channel type gate array, but in recent years, an all-over type gate array with a different architecture has been attracting attention. This is discussed in the Proceedings of IE E. Custom Integrated Circuits Conference (May 20-23, 1985), pages 15 to 17.
E L 985Custon+ Integrat
ed C1rcuits Conterence). The all-over type is a type in which basic cells are arranged over the entire internal area of the chip, maximizing the feature of variable channel area and increasing the actual number of gates. This will be explained using the master chip configuration shown in FIG. In a peripheral area 51 on the chip 50, an external cell 52 including a single output puffer and a bonding pad (not shown) are arranged.

Basic cells 53 are spread over the entire surface of the internal region 54. Therefore, the wiring channels can be selected in units of the height of the basic cell or, by providing symmetry to the basic cell as described in the above-mentioned literature, in units of half the height of the basic cell. High-density packaging becomes possible.

Additionally, large macrocells can be mounted at a much higher density than conventional fixed channel systems, which is highly effective.

In FIG. 6, ROM and RAM.

In addition to the PLA macrocell, ALU and analog super tuna were also shown. In the full-coverage type, the macrocells can be freely arranged and have variable capacitance, making them suitable for use in gate arrays.

The present invention provides a programmable CMOS logic array particularly suitable for this all-over gate array.

[Problems that the invention attempts to solve]

The above-mentioned conventional technology does not take into account ease of design change, versatility, and miniaturization, and has problems that are particularly inappropriate when adopting a CMO3 structure cell structure such as a gate array.

An object of the present invention is to provide a programmable CMOS that can be miniaturized by matching cells with a CMO3 structure such as gate arrays, and that can be easily expanded into macro cells using DA (Design Antomation) according to the capacity specified by the user. The purpose is to provide logic arrays.

Means for Solving Problems c] The present invention provides a horizontal PLA circuit in which an AND matrix is connected in parallel between each output signal line and one power supply line, each of one MPO8 (or NMOS), and It consists of a load MO8 connected between the erroneous output signal line and the other power supply line, and the OR matrix is composed of one NMOS (or PMOS), and a load MO8 connected between the erroneous output signal line and one power supply line, and the PMO5.

Input signal lines corresponding to the gate electrodes of the NMOS are separated and arranged, and logic programming is performed by connecting them with a wiring layer mask.

A PLA circuit with n input signals, Q terms, and n output signals is shown in FIG. 1, illustrating the principle of the present invention. This PLA circuit is ORed with the A N D matrix 100.
It is composed of a matrix 101. This A
The N D matrix 100 has an inverter D Ro=
D Ro-t, load NMOSNT, o”-N L
s -x + output driver RF o-B F t-i
and nXQ PMOSs.

On the other hand, the OR matrix 101 has the load PMO3PLo
~PI,. -1, output driver OB=OB, -1.

and Xm 8MO8s.

As is clear from the above configuration, in the present invention.

The number of PMOS (NMOS) is 1 person, 1 per term, and the number of 8MO8 (PMO5) is 1 per term, 1 output.
Since it only requires 1000 pcs, compared to the conventional CMOS static type, M
The number of OSs can be halved.

Note that in this configuration, a large number of PMO3 or 8MO8 are connected between the output point and the power supply line, so the load MO5 needs to be designed in consideration of the ratio.

In the gate array, since the lMOS size is uniform, a large number of M
This ratio design is performed by connecting the OSs in series; FIG. 1 shows one MOS for convenience. Also, load MO
By controlling the resistance No. 5, it is possible to make a trade-off between power consumption and operating speed.

[Effect]

Next, the present invention will be explained in detail. First, in the AND array, n PMOSs each having a VCc power source electrode connected to the same output signal XjATJ' are connected to the same output signal XjATJ' corresponding to each input signal line I o - I n -t. The gate electrode 8 of each PMO 3 is separated from the input signal line, and is connected to the desired Il or end by drilling a contact hole at the position indicated by 9' (indicated by an X in FIG. 1). Connected.

Tt' is the input signal Io-Ins (Io-I
n-1), N A N D logic output, Tt is AN
It is a D logic output. In the case of FIG. 1, the following logical formula is programmed.

To= I o ・I x・= I n-1T engineering= I
o ・I s=・I n-1'rz= I o-I
n-1 T3= I s・= I n-t 7, -2= I n-1 Tt-1= I o' I x・= I −-1 Next, in the OR array 101, each term M T .

~ Corresponding to T m -s, to the same output signal line 01',
Q 8 MO8s whose source electrodes are connected to the GND power source are connected. In this case as well, the gate electrode of each NMOS is aligned with the desired term line T by forming a contact hole at the position indicated by 9'.

Connect to. OL' is an input signal (term signal) T.

It has the function of a NOR gate for ~T x -t.

Looking at the output signal lines of the output drivers OB+ to ○Bn-t, the whole becomes an OR array.

As explained above, according to the present invention, the gate electrode is
(II), that is, it is possible to change only the wiring pattern. Also.

According to the present invention, if there is no difference in the number of input signals and the number of output signals, the number of PMOS and NMOS used can be almost the same, and when configured with basic cells like a gate array, the implementation rate can be improved. Can be done.

Furthermore, according to the present invention, it is possible to create a unit PLA cell in which an AND matrix and an OR matrix are integrated.
This has the effect of improving packaging density and facilitating macro cell deployment by DA.

〔Example〕

Examples of the present invention will be described below.

FIG. 7 shows an embodiment of the invention.

In this embodiment, a PLA macro cell according to the present invention is constructed in an all-over gate array in which the basic cells shown in FIGS. 4 and 5 are spread over the entire chip internal region. In Figure 7, one point It! 53 indicated by a line is a basic cell consisting of four PuO8, MMC:S pairs,
They are arranged in parallel in the X-axis and Y-axis directions. Logic cells and macrocells made of wiring patterns are placed on this base to obtain the desired electrical rotation. The wiring pattern in the block 53, that is, the logic cell is an AND/OR integrated unit cell (
2 manual power, 2 terms, 2 outputs), 203 is output driver○
201 is a block configuring the output driver B F o-B F t-1, 202 is a load N each consisting of two series-connected NMOS
The block 204 constituting the MOS, NLo"NLa-s is composed of m/2 integrated unit cells in the X-axis direction and n/2 or m/2 integrated unit cells in the Y-axis direction.
M! This is a PLA matrix block consisting of S. In addition, in the wiring pattern shown in Figure 7, the solid line is the first layer aluminum (AQl), and the broken line is the second layer aluminum (Af1).
2) The mark X is a contact hole for connecting the diffusion layer or poly-Si and AQL, and the mark O is a contact hole opened in the middle of the layer to connect AQl and AQ2. In order to connect the diffusion layer or poly-Si to AQ2, first make contact holes x and 0 at the corresponding locations to connect both to the AQI.
You can connect it with

Of the four PuO8s in the basic cell 53, two each are Vc
Between the ct source and the output signal lines To' and T'.

Source and drain are connected. In other words, the two PuO3 trains on the left are on the To' side, and the two PuO3 trains on the right are on the To' side.
The O8 train is connected to the Tt' side. The To' signal line Tl/signal line is wired in the Y-axis direction using Au2, and connected to the gate electrode of the output driver block 201 arranged on its extension. The output driver has two P
It consists of a parallel connection configuration of uO2 and a parallel connection configuration of two NMOS, forming a power driver. Therefore, 1
Two power drivers can be formed with a basic cell, and T o/
, T1/ , T, / , T, / can match the pitch of the power driver array. At the same time, To/, 11-11' is the load NMOS block 20
2 and pulled down by two NMOSs connected in series with their gate electrodes fixed to the Vcc power supply. In this case as well, the pitch of To' and Tl' can be made to match the arrangement pitch of the load NMOS cells.

On the other hand, the output signal 'l1AOt' of the OR matrix has a source of G among the four NMO5s in the same basic cell.
The common drains of each of the two NMOSs connected to the NDffi potential line are commonly connected through the contact hole x,
It is wired in the X-axis direction on the NMOS in the same basic cell.

That is, the output signal line ○/, 01'.

02', 03'... constitute NOR gate outputs.

However, the output signal! M for pull-up connected to Ot'
The OS cell is not shown. Output signal line Oo.

011 C) z+ 03+ ... is via the output dry pulse cell 203, so the term input To+ Ti
It becomes an OR logic output for p T21T86
The logic program is executed as follows. First, AND
Explain the matrix. However, the left P of the two PM6 S connected to the same output signal line TI'
It is assumed that uO8 is for input signal lines Ij and Ij, and PuO2 on the right side is for input signal lines I J+11 I J+1.

Logic programming is performed by connecting a predetermined input signal line to the gate ff electrode of PuO3. This connection pattern is formed by an X-marked contact hole and an Al21 wiring layer.

The connection pattern described above is shown in FIG. 7 by thick solid lines and the contact holes. In addition.

In the above program, for MOS that does not take logic, it is necessary to fix the gate electrode to Vcc or GND potential.
These wiring patterns are omitted in FIG. 7 for the sake of simplicity. The various wiring patterns described above can be prepared, for example, as several types of cells (called modified cells) for one basic cell, and arranged in a matrix according to the logic program specifications. It has a feature that makes it easy to automatically expand and generate macro cells.

Note that the operation is the same as that shown in FIG. 1, so a description thereof will be omitted.

FIG. 8 is a block diagram showing one embodiment of FIG. 7. The PLA macrocell has input buffer blocks 210 . ANDloR integrated unit cell 53. Output driver block 201゜A N D matrix load M
OS block 202, output driver block 203,
and an OR matrix load MOS block 211. Numerical values and symbols in the figure represent the number of basic cells in the X-axis direction and the number (stage number) in the Y-axis direction. Therefore, if the number of input signals is 1, the number of terms is α, and the number of output signal lines is m, the size of the PLA macrocell is (n / 2 + 3) X n / 2, or (Q / 2 + 3) It becomes X m/2.

The cell structure of the unit cell 523 is shown in FIG. this is,
This shows the relationship between the 53 input and output signals in Figure 7, and the input signal line 1-1 is constructed using AQl in the unit cell.
TI and output signal line ○l-1,01 run in the X-axis direction, and term line TJ-1, AQ2 in the Y-axis direction.

T is running.

In this manner, in this embodiment, since the control wiring passes over the MOS transistor, the packaging density can be increased.

FIG. 10 shows another embodiment, and shows an A N D matrix circuit. However, the 0 AND logic section showing only the AND logic section of term TI is PMO3Po, Pt-
Pn-z+NMOSNLoo+N Lol, N Lazy that configures the output driver BFi and the load NMO3
Consists of NLO3. This embodiment is an improved version of the load MO8, and the other configurations and operations are the same as the embodiment described above, so explanations will be omitted.

The load MO5 according to this embodiment is composed of four NMOSs whose gate electrodes are connected to the output signal line T% and whose sources and drains are connected in series. Output signal line T,'
(73'1' t/bell voltage VOH is about 2 to 3 V depending on the ratio of PMO5 to load NMO3.

Therefore, the voltage level of gated 1 of the NMO3 is 2.
~3V, the resistance of the NMOS increases, and the DC current consumption can be reduced.

〔Effect of the invention〕

According to the present invention, an AND matrix and an OR matrix can be formed using MO8s that are complementary to each other, and a layout configuration in which both matrices are integrated is possible.
It is possible to form a PLA using 8 cells in a small size, and it is easy to expand and generate a PLA macro cell using DA (Desjg~Automation). especially,
There is a great effect when a PLA macrocell is formed with a gate array with gates all over the surface.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing the principle of the present invention, Fig. 2 is a chip plan view showing a conventional example, Figs. 3 and 4 are plan views showing basic cell examples, and Fig. 5 is a pattern diagram of the basic cell. , FIG. 6 is a chip plan view of a fully gated date array, FIG. 7 is a wiring diagram showing an embodiment of the present invention, FIG. 8 is a block diagram supplementing FIG. 7, and FIG. 8 is a block diagram supplementing FIG. 8, and FIG. 10 is a circuit diagram showing another embodiment. 100...AND matrix, 101...OR matrix, 201, 203...output driver block, 202...load MOS block.

Claims (1)

[Claims] 1. n PMOSs connected in parallel between n positive input signal lines, inverted input signal lines, at least one output signal line, a power supply line, and the output signal line. (or NMOS) transistor, and a resistance element or load MOS transistor connected between the output line and ground,
The input signal lines corresponding to the gate electrodes of the PMOS (or NMOS) transistors are arranged in an open state, and if necessary, connected to either of the positive or inverted input signals using a wiring layer mask to perform a logic program. A programmable CMOS logic array featuring: 2. In the product described in claim 1, at least two PMs whose sources or drains are connected in series
A logic array/macrocell is constructed using a CMOS gate array in which basic cells are regularly arranged on a chip, each consisting of an OS transistor and at least two NMOS transistors whose sources or drains are connected in series, and which are arranged relative to each other. PMOS, NMOS in the basic cell
A programmable CMOS logic array characterized in that it is formed using transistors as an AND array, an OR array, an OR array, and an AND array, respectively. 3.AND array and. An OR array includes n positive input signal lines, inverted input signal lines, at least one output signal line, and n PMOS (or NMOS) transistors connected in parallel between a power supply line and the output signal line. and a resistance element or a load MOS transistor connected between the output line and ground, and the input signal line corresponding to the gate electrode of the PMOS (or NMOS) transistor is arranged in an open state. , if necessary, connect it to either of the positive or inverted input signal lines using a wiring layer mask, and configure X output signal lines (number of terms) of PMOS (
or NMOS) transistor and load resistance element, OR
The array is (number of terms) x (number of output signal lines) NMOS (
A programmable CMOS logic array characterized in that it is formed by a PMOS (or PMOS) transistor and a load resistance element. 4. In the product described in claim 3, at least two Ps whose sources or drains are connected in series
A logic array/macrocell is constructed using a CMOS gate array in which basic cells each consisting of a MOS transistor and at least two NMOS transistors whose sources or drains are connected in series are arranged regularly on a chip. together with PMOS and NMOS in the basic cell
A programmable CMOS logic array characterized in that it is formed using transistors as an AND array, an OR array, an OR array, or a NAD array.