JPH04246858A - Gate array semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a gate array type semiconductor integrated circuit enhanced in degree of freedom of circuit constitution by a method wherein two kinds of basic cells composed of first and second basic cells are arranged regularly in over a row. CONSTITUTION:One or more basic cells composed of cells 1 or cells 2 are arranged in a lateral direction on a semiconductor chip 11 to constitute a basic cell row, and basic cell 1 rows and basic cell 2 rows are alternately arranged in a longitudinal direction. By this constitution, when a drive capacity is enhanced, the cells 2 are used, whereby a few basic cells used in a case where only the cells are used are not required to be used, and a required logic circuit can be realized. When a transistor is low in drive capacity, the cells 1 are used, whereby a semiconductor integrated circuit of this design can be more enhanced in operation speed than a case where only the cells 2 are used.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a gate array type semiconductor integrated circuit device.

0002

2. Description of the Related Art In a conventional gate array type semiconductor integrated circuit device, a basic cell 43 (hereinafter referred to as cell type 1) consisting of a CMOS transistor as shown in FIG.
As shown in FIG. 4, a basic cell 44 (hereinafter referred to as cell type 2) consisting of a combination of bipolar transistors and CMOS transistors as shown in FIG. One or more of them are arranged both horizontally and vertically on the semiconductor chip 31.

0003

[Problems to be Solved by the Invention] In the conventional gate array type semiconductor integrated circuit device described above, for example, in the case of a semiconductor chip consisting of only cell type 1, it is necessary to use a transistor with high drive ability in a desired circuit. When designing, use one or more basic cells. For that reason,
In the case of a circuit configuration having many transistors with high drive ability, there is a drawback that too many basic cells prepared in advance are used, making it impossible to realize a desired logic circuit.

On the other hand, in the case of a semiconductor chip composed of cell type 2, the cell size of the basic cell is larger than that of CMOS, the number of cells on the semiconductor chip is reduced, and the semiconductor chip composed of cell type 2 In this case, when designing a transistor with low drive capability in the desired circuit configuration, cell type 1 basic cells are faster, so cell type 2 is used.
It also has the disadvantage that the speed of configuration is slow.

An object of the present invention is to provide a gate array type semiconductor integrated circuit device that increases the degree of freedom in circuit configuration.

[0006]

[Means for Solving the Problems] A gate array type semiconductor integrated circuit device of the present invention has two basic cells: a basic cell consisting only of CMOS transistors, and a basic cell consisting of a combination of bipolar transistors and CMOS transistors. The direction is a basic column in which one or more basic cells of the same type are arranged, and the vertical direction is a basic cell column consisting of only CMOS transistors and one or more basic cell columns consisting of a combination of bipolar transistors and CMOS transistors with regularity. It is located.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a configuration diagram of an embodiment of the present invention. In the horizontal direction of the semiconductor chip 11, one or more basic cells of the same type of cell type 1 or cell type 2 shown in FIGS. 3(a) and 3(b) are arranged to constitute a basic cell row, and in the vertical direction, the cells are 1 basic cell column of type 1 and 1 basic cell column of cell type 2 alternately
Create a configuration with more than one. (The same applies when the basic cell is rotated by 90 degrees.) With this configuration, if you want to increase the drive capacity in the desired circuit, you can use cell type 2 and only cell type 1. It is no longer necessary to use several basic cells as was the case when the logic circuit was configured with , making it possible to realize the desired logic circuit.

Furthermore, in the case of a transistor with low drive ability, by using cell type 1, the speed becomes faster than when it is configured with only cell type 2.

FIG. 2 is a block diagram of a second embodiment of the present invention. In the horizontal direction of the semiconductor chip 21, a basic cell row is formed by arranging one or more basic cells of the same type of cell type 1 or cell type 2, and in the vertical direction, three basic cell rows of cell type 1 are arranged.
Next, place one basic cell column of cell type 2,
Construct it by repeating it. (The same applies when the basic cell is rotated by 90 degrees.) With this configuration,
When designing blocks such as 8-bit shift registers and counters, the final stage transistor of the block should be set to cell type 2.
It is possible to configure other transistors with cell type 1, and there is an advantage that cell type 1 and cell type 2 can be used efficiently during block design.

0010

As explained above, in the present invention, cell type 1 and cell type 2 are horizontally arranged as basic cell rows in which several basic cells of the same type are arranged, and vertically as basic cell rows of cell type 1. By arranging basic cell rows of cell type 2 every few cells, when designing a transistor with high drive ability, by using cell type 2, it is possible to configure it with a minimum number of basic cells, and, When designing a transistor with low drive ability, using cell type 1 increases speed.

[0011] Furthermore, by configuring basic cells of the same type in the horizontal direction, the height of the basic cells in the horizontal direction becomes uniform, which has the effect of improving the efficiency of wiring that connects circuits of a desired circuit that is automatically designed. be.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a semiconductor chip showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a semiconductor chip showing a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a basic cell.

FIG. 4 is a configuration diagram of a semiconductor chip showing a conventional example.

[Explanation of symbols]

11, 21, 31 semiconductor chip 12, 22, 3
2 Input/output buffer 13, 23 CMOS
Basic cell row consisting only of transistors (basic cell row of cell type 1) 14, 24 Bipolar transistor and CMOS
Basic cell row composed of a combination of transistors (basic cell row of cell type 2) 43 Basic cell composed of only CMOS transistors (cell type 1)

Claims (2)

[Claims] Claim 1: The first and second basic cells are basic columns in which one or more of the same type of basic cells are arranged in one direction, and the first and second basic cells are basic cells arranged in one direction.
A semiconductor integrated circuit device of a gate array type, characterized in that one or more two types of basic cell rows consisting of a second basic cell and a second basic cell are arranged with regularity. 2. The gate array system according to claim 1, wherein the first basic cell is composed of a CMOS transistor, and the second basic cell is composed of a combination of a bipolar transistor and a CMOS transistor. semiconductor integrated circuit devices.