JPH01166536A - Mos type semiconductor device - Google Patents
Mos type semiconductor deviceInfo
- Publication number
- JPH01166536A JPH01166536A JP32570187A JP32570187A JPH01166536A JP H01166536 A JPH01166536 A JP H01166536A JP 32570187 A JP32570187 A JP 32570187A JP 32570187 A JP32570187 A JP 32570187A JP H01166536 A JPH01166536 A JP H01166536A
- Authority
- JP
- Japan
- Prior art keywords
- type
- gate electrode
- gate
- semiconductor integrated
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- 239000007772 electrode material Substances 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- 239000012212 insulator Substances 0.000 abstract description 3
- 238000003491 array Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004575 stone Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、MO8型半導体装置に関し、特に半導体集積
回路のゲートアレイのベーシックセルのゲート電極での
ダイオード素子の実現に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an MO8 type semiconductor device, and particularly to the realization of a diode element in a gate electrode of a basic cell of a gate array of a semiconductor integrated circuit.
従来の半導体集積回路のゲートアレイのベーシックセル
においては、寄生ダイオードが存在しない純粋なダイオ
ード素子が組み込まれたものはなかった。また、従来の
半導体集積回路のゲートアレイのベーシックセルの大半
は、ゲート電極の極性が同じである同極性のポリシリコ
ンをゲート電極材料としたP型MO3?ETとN型M″
osFFXTとにより構成されていた。No conventional basic cell of a gate array of a semiconductor integrated circuit incorporates a pure diode element without a parasitic diode. In addition, most of the basic cells of gate arrays of conventional semiconductor integrated circuits are P-type MO3? whose gate electrodes are made of polysilicon with the same polarity as the gate electrode material. ET and N type M''
It was composed of osFFXT.
今日、半導体集積回路のゲートアレイにおいて、ゲート
アレイ内部にアナログ回路を組み込む傾向が著しく、ま
た、アナログ回路においてはその大半にダイオード素子
が不可決なものとなっており、ゲートアレイ内部にダイ
オード素子を組み込む必要性が高まっている。ひいては
、ゲートアレイ内部のベーシックセルのゲー)?4を極
において、ダイオード素子を実現することができれば、
ゲート電極は絶縁物によって囲まれている為、寄生ダイ
オード等の問題もなく、純粋にダイオード素子として利
用することができる。Today, in gate arrays of semiconductor integrated circuits, there is a remarkable tendency to incorporate analog circuits inside the gate array, and in addition, diode elements have become essential in most of the analog circuits. There is an increasing need to incorporate By extension, the basic cells inside the gate array)? If it is possible to realize a diode element using 4 as a pole,
Since the gate electrode is surrounded by an insulator, it can be used purely as a diode element without problems such as parasitic diodes.
しかし、前述の従来のゲート電極の極性が同じである同
極性のポリシリシンをゲート電極材料としたP型M石5
IFI!tTとN型M万SνETによって構成されてい
た半導体集積回路のゲートアレイのベーシックセルにお
いては、ゲート電極でダイオード素子を構成することが
できなかった。However, the P-type M stone 5 uses polysilisine of the same polarity as the gate electrode material of the conventional gate electrode described above.
IFI! In a basic cell of a gate array of a semiconductor integrated circuit, which is constituted by tT and N-type M10,000SvET, a diode element cannot be constituted by the gate electrode.
そこで、本発明は以上の如き種々の事情に鑑みなされた
もので、その目的とするところは、半導体集積回路のゲ
ートアレイのベーシックセルのゲート電極でのダイオー
ド素子の実現にある。SUMMARY OF THE INVENTION The present invention was developed in view of the various circumstances described above, and its object is to realize a diode element in a gate electrode of a basic cell of a gate array of a semiconductor integrated circuit.
本発明のMOS型半導体装置は、
α)半導体集積回路のゲートアレイにおいて、b)P型
ポリシリコンをゲート電極材料とするP型MO3IFE
Tと、N型ポリシリコンをゲート電極材料とするN型M
石5FETとを含み、かつ、前記P型M百5IFI!i
Tのゲート電極と、前記N型MO8IFKTのゲート電
極とが接していることから成るベーシックセルな有し、
C)かつ、少なくともひとつの前記ベーシックセルにお
いて、前記P型Mで5IFETのゲート電極と、前記N
型MO8IFETのゲート電極とに端子取り出し口を設
けたことを特徴とする。The MOS type semiconductor device of the present invention includes α) a gate array of a semiconductor integrated circuit, b) a P-type MO3IFE using P-type polysilicon as a gate electrode material;
T, and N-type M whose gate electrode material is N-type polysilicon.
5FETs, and the P-type M15IFI! i
C) and in at least one of the basic cells, the gate electrode of the P-type M5IFKT is in contact with the gate electrode of the N-type MO8IFKT; Said N
It is characterized by providing a terminal outlet at the gate electrode of the MO8IFET.
第1図に、本発明のMO8型半導体装置の基本的な実施
例の平面図を示す。FIG. 1 shows a plan view of a basic embodiment of an MO8 type semiconductor device of the present invention.
斜めハツチ部により示される101は、P型ポリシリコ
ンゲート電極であり、1o2は、前記101をゲート電
極としてP型M百8?]!f’l’を形成する。クロス
ハツチ部により示される103は、N型ポリシリコンゲ
ート電極であり、104は、前記104をゲート電極と
し0型MO871Tを形成する。前記102の101と
104の103を接することで、半導体集積回路のゲー
トアレイのベーシックセルな形成する。さらに、前記1
02の101と104の103とに、105のコンタク
トホールと106のアルミとにより端子取り出し口を設
ける。101 indicated by the diagonal hatch is a P-type polysilicon gate electrode, and 1o2 is a P-type M18? with 101 as the gate electrode. ]! form f'l'. Reference numeral 103 indicated by a crosshatch is an N-type polysilicon gate electrode, and reference numeral 104 forms a 0-type MO871T using the above-mentioned 104 as a gate electrode. By touching 101 of 102 and 103 of 104, a basic cell of a gate array of a semiconductor integrated circuit is formed. Furthermore, the above 1
A terminal outlet is provided at 101 of 02 and 103 of 104 by a contact hole 105 and aluminum 106.
この結果、半導体集積回路のゲートアレイのベーシック
セルのゲート電極でダイオード素子を実現できる。As a result, a diode element can be realized using the gate electrode of a basic cell in a gate array of a semiconductor integrated circuit.
以上、基本的な実施例について説明をしたが、上記実施
例に限らず、ベーシックセルの形を変えた場合において
も同様な事が言え、さらに、ゲート電極以外に配線に使
用するポリシリコンにおいても、P型ポリシリコンとN
型ポリシリコンを接したポリシリコンを適用し、端子取
り出し口を設けることにより同様な事が言える。The basic embodiments have been explained above, but the same applies not only to the above embodiments but also when the shape of the basic cell is changed.Furthermore, the same applies to polysilicon used for wiring other than gate electrodes. , P-type polysilicon and N
The same thing can be said by applying polysilicon in contact with mold polysilicon and providing a terminal outlet.
本発明の効果は、半導体集積回路のゲートアレイにおい
て、前述の機なベーシックセルを適用し、ゲート電極に
端子取り出し口を設けることによりベーシックセルのゲ
ート電極でダイオード素子を実現することができる。こ
の結果、ゲート電極は絶縁物によって囲まれている為、
寄生ダイオードの存在しない純粋なダイオード素子を実
現することができ、前記ダイオード素子は、ゲートアレ
イ内部にアナログ回路を組み込む際に有効なものとなっ
た。The effect of the present invention is that by applying the above-described sophisticated basic cell to a gate array of a semiconductor integrated circuit and providing a terminal outlet in the gate electrode, a diode element can be realized with the gate electrode of the basic cell. As a result, the gate electrode is surrounded by an insulator, so
A pure diode element without any parasitic diodes can be realized, and the diode element becomes effective when incorporating an analog circuit inside a gate array.
第1図は、本発明のMOB型半導体装置の基本的が実施
例を示す平面図。
101・・・・・・P型ポリシリコンゲート電極(斜め
ハツチ部)
102 ・−・・・P型MO8?ET
103・・・・・・N型ポリシリコンゲート′Di極(
クロスハツチ部)
104・・・・・・N型MO5PET
105・・・・・・コンタクトホール
106・・・・・・アルミ
以上
出願人 セイコーエプソン株式会社
第1図FIG. 1 is a plan view showing a basic embodiment of the MOB type semiconductor device of the present invention. 101...P-type polysilicon gate electrode (diagonal hatch part) 102...P-type MO8? ET 103...N-type polysilicon gate 'Di pole (
Cross hatch part) 104... N type MO5PET 105... Contact hole 106... Aluminum or above Applicant Seiko Epson Corporation Figure 1
Claims (1)
O@STETと、N型ポリシリコンをゲート電極材料と
するN型M@O@SFETとを含み、かつ、前記P型M
@O@SFETのゲート電極と、前記N型M@O@SF
ETのゲート電極とが接していることから成るベーシッ
クセルを有し、 c)かつ、少なくともひとつの前記ベーシックセルにお
いて、前記P型M@O@SFETのゲート電極と、前記
N型M@O@SFETのゲート電極とに端子取り出し口
を設けたことを特徴とするM@O@S型半導体装置。(1) a) In a gate array of a semiconductor integrated circuit, b) P-type M@ with P-type polysilicon as the gate electrode material
O@STET and N-type M@O@SFET using N-type polysilicon as a gate electrode material, and the P-type M
The gate electrode of @O@SFET and the N-type M@O@SF
c) and in at least one of the basic cells, the gate electrode of the P-type M@O@SFET and the N-type M@O@SFET are in contact with each other; An M@O@S type semiconductor device characterized in that a terminal outlet is provided at the gate electrode of an SFET.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32570187A JPH01166536A (en) | 1987-12-23 | 1987-12-23 | Mos type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32570187A JPH01166536A (en) | 1987-12-23 | 1987-12-23 | Mos type semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01166536A true JPH01166536A (en) | 1989-06-30 |
Family
ID=18179744
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32570187A Pending JPH01166536A (en) | 1987-12-23 | 1987-12-23 | Mos type semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01166536A (en) |
-
1987
- 1987-12-23 JP JP32570187A patent/JPH01166536A/en active Pending
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