JPH0319285A - Mos type semiconductor device - Google Patents

Mos type semiconductor device

Info

Publication number
JPH0319285A
JPH0319285A JP15344989A JP15344989A JPH0319285A JP H0319285 A JPH0319285 A JP H0319285A JP 15344989 A JP15344989 A JP 15344989A JP 15344989 A JP15344989 A JP 15344989A JP H0319285 A JPH0319285 A JP H0319285A
Authority
JP
Japan
Prior art keywords
gate
channel
polysilicon film
type
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15344989A
Other languages
Japanese (ja)
Inventor
Mikio Kishimoto
岸本 幹夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP15344989A priority Critical patent/JPH0319285A/en
Publication of JPH0319285A publication Critical patent/JPH0319285A/en
Pending legal-status Critical Current

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  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To obtain a MOS device having high drain current driving capacity by providing a polysilicon film on a gate thereby to form a channel in the film. CONSTITUTION:When a voltage of Vth or more is applied to a gate 3, a P-type Si substrate 1 under the gate 3 is inverted to an N type, and an N channel 7a is formed. Simultaneously, a P-type polysilicon film 5 on the gate is inverted to an N-type, and an N channel 7b is formed. When a positive voltage is applied to a lower drain region 4a and an upper drain region 6a in this state, drain currents flow from a lower source 4b through the channel 7a to the lower drain 4a and from an upper source 6b through the channel 7b to an upper source 6b. Channels 7a, 7b are not formed by the application of the voltage to the gate 3, and no drain current flows. A large quantity of drain current can flow with this arrangement.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、MOS型半導体装置に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a MOS type semiconductor device.

従来の技術 近年、半導体装置の高集積化に伴う低消費電力の要求か
ら、MOS型半導体装置が活発に開発されている。
2. Description of the Related Art In recent years, MOS type semiconductor devices have been actively developed to meet the demand for lower power consumption as semiconductor devices become more highly integrated.

以下に従来のMOS型半導体装置について第2図によシ
説明する。
A conventional MOS type semiconductor device will be explained below with reference to FIG.

第2図にかいて、11はp型シリコン基板、12は酸化
膜、13はポリシリコン膜によるゲート、14aはn型
不純物拡散層によるドレイン領域、14bはn型不純物
拡散層によるソース領域、そして17はp型シリコン基
板が反転して形威されるnチャンネルである。
In FIG. 2, 11 is a p-type silicon substrate, 12 is an oxide film, 13 is a gate made of a polysilicon film, 14a is a drain region made of an n-type impurity diffusion layer, 14b is a source region made of an n-type impurity diffusion layer, and 17 is an n-channel formed by inverting a p-type silicon substrate.

以上のように構戒されたMOS型半導体装置について、
以下その動作を説明する。
Regarding the MOS type semiconductor device with the above precautions,
The operation will be explained below.

寸ず、ゲート電極13に、しきい値を超える電圧を印加
すると、p型シリコン基板11のゲート13下部分がn
型に反転し、伝導電子が自由に通過できるnチャンネル
17が形或される。従って、このnチャンネル17が形
威された状態で、ドレイン領域14aに正電圧を印加す
ると、伝導電子はnチャンネルを通ってソース領域14
bからドレイン領域14aにドレイン電流が流れる。と
ころがゲート13に印加する電圧が零の状態ではnチャ
ンネル17が形或されていなしため、ドレイン電流は流
れなー。このようにゲート13に印加する電圧を変化さ
せることで、ドレイン電流を制御できる。
When a voltage exceeding the threshold value is applied to the gate electrode 13, the lower part of the gate 13 of the p-type silicon substrate 11 becomes n
The mold is inverted, forming an n-channel 17 through which conduction electrons can freely pass. Therefore, when a positive voltage is applied to the drain region 14a with this n-channel 17 formed, conduction electrons pass through the n-channel to the source region 14a.
A drain current flows from b to drain region 14a. However, when the voltage applied to the gate 13 is zero, the n-channel 17 is not formed, so no drain current flows. By changing the voltage applied to the gate 13 in this way, the drain current can be controlled.

発明が解決しようとする課題 しかしながら、上記の従来の構戒では、nチャンネルが
形或される部分がゲート下p型シリコン基板部分のみで
あったので、高集積回路に用いられるような、微小面積
のMOS型半導体装置では、大量のドレイン電流を流す
ことができないという問題点を有していた。
Problems to be Solved by the Invention However, in the above-mentioned conventional structure, the part where the n-channel is formed is only the p-type silicon substrate part under the gate. The MOS type semiconductor device has a problem in that a large amount of drain current cannot flow through it.

本発明は上記従来の問題点を解決するもので、面積を増
大させずに、よう多くのドレイン電流を得ることのでき
るMOS型半導体装置を提供することを目的とするもの
である。
The present invention solves the above-mentioned conventional problems, and aims to provide a MOS type semiconductor device that can obtain a large amount of drain current without increasing its area.

課題を解決するための手段 この目的を達或するために本発明のMOS型半導体は、
ゲートの上にゲートと絶縁されたポリシリコン膜を形成
することによう、半導体基板内のチャンネルに加えて、
ゲートの上のポリシリコン膜中にもチャンネルが形或で
きる構成を有している。
Means for Solving the Problems In order to achieve this object, the MOS type semiconductor of the present invention is as follows:
In addition to the channel in the semiconductor substrate, a polysilicon film insulated from the gate is formed on top of the gate.
It has a structure in which a channel can also be formed in the polysilicon film above the gate.

作  用 本発明の構成によれば、ゲートにしきい値以上の電圧を
印加することで得られるnチャンネルが、ゲート下のシ
リコン基板、およびゲート上のポリシリコン膜の双方の
層に形威されるため、ドレイン電流量を増すことができ
MOS型半導体装置の電流駆動能力を向上することがで
きる。
According to the configuration of the present invention, an n-channel obtained by applying a voltage higher than a threshold value to the gate is formed in both layers of the silicon substrate under the gate and the polysilicon film on the gate. Therefore, the amount of drain current can be increased, and the current drive capability of the MOS type semiconductor device can be improved.

実施例 以下本発明によるMOS型半導体装置を第1図を参照し
ながら説明する。
EXAMPLE A MOS type semiconductor device according to the present invention will be described below with reference to FIG.

第1図にかいて、1はp型シリコン基板、2は酸化膜、
3はポリシリコン膜によるゲート、4aはシリコン基板
内1c.n型不純物拡散層による下部ドレイン領域、そ
して、4bはシリコン基板内型物拡散層による上部ドレ
イン領域、6bはポリシリコン膜内n型不純物拡散眉に
よる上部ソース領域、7aはp型シリコン基板が反転し
て形或されるnチャンネル、そして7bはp型ポリシリ
コン膜が反転して形或されるnチャンネルである。
In Figure 1, 1 is a p-type silicon substrate, 2 is an oxide film,
3 is a gate made of a polysilicon film, 4a is a gate 1c in a silicon substrate. A lower drain region formed by an n-type impurity diffusion layer, 4b an upper drain region formed by a silicon substrate-internal dopant diffusion layer, 6b an upper source region formed by an n-type impurity diffusion layer in a polysilicon film, and 7a a p-type silicon substrate reversed. 7b is an n-channel formed by inverting the p-type polysilicon film.

以上のように構成された本実施例のMOi9型半導体装
置について、以下その動作を説明する。
The operation of the MOi9 type semiconductor device of this embodiment configured as described above will be described below.

まず、ゲート3に、しきい値を超える電圧を印加すると
、p型シリコン基板1のゲート3下がn型に反転し、伝
導電子の自由に通過できるnチャンネル7aが形或され
る。筐た同時に、ゲート上のp型ポリシリコン膜5もn
型に反転し、nチャンネル7bが形或される。従って、
このnチャンネル7aiよび7bが形或された状態で、
下部ドレイン領域4a′J?よび上部−ドレイン領域6
aに正電圧を印加すると、伝導電子はnチャンネル7a
を通って下部ソース領域4bから下部ドレイン領域4a
へ、そしてnチャンネル7bを通って上部ソーぶ領域6
bから下部ドレイン領域6aへ、それぞれの経路によシ
ドレイン電流が流れる。ところが、グート3に印加する
電圧が零の状態ではnチャンネル7aおよび7bが形成
されていないためドレイン電流は流れ々い。
First, when a voltage exceeding a threshold value is applied to the gate 3, the portion of the p-type silicon substrate 1 below the gate 3 is inverted to the n-type, forming an n-channel 7a through which conduction electrons can freely pass. At the same time as the case, the p-type polysilicon film 5 on the gate is also
The mold is inverted to form an n-channel 7b. Therefore,
With these n channels 7ai and 7b formed,
Lower drain region 4a'J? and top-drain region 6
When a positive voltage is applied to a, conduction electrons are transferred to n-channel 7a
from the lower source region 4b to the lower drain region 4a through the
to the upper saw region 6 through the n-channel 7b.
A side drain current flows from the lower drain region 6a to the lower drain region 6a through each path. However, when the voltage applied to the groove 3 is zero, the n-channels 7a and 7b are not formed, so the drain current does not flow much.

以上のように本実施例によれば、ゲート下半導体基板内
のnチャンネルに加え、ゲートの上にnチャンネルが形
戒できるポリシリコン膜を有する構成にしたことによう
、大量のドレイン電流を流すことができる。
As described above, according to this embodiment, in addition to the n-channel in the semiconductor substrate under the gate, the polysilicon film is formed above the gate so that a large amount of drain current can flow. be able to.

なお、本実施例では、nチャンネル形或のため、シリコ
ン基板かよびゲート上ポリシリコン膜tp型、そして、
ソース領域およびドレイン領域形或のための拡散層をn
型としたが、pチャンネル形成のために、シリコン基板
およびゲート上ポリシリコン膜をn型、そして、ソース
領域およびドレイン領域形成のための拡散層をp型とし
てもよい。
In addition, in this example, since it is an n-channel type, a silicon substrate, a tp type polysilicon film on the gate, and
The diffusion layer for the source and drain regions is
However, in order to form a p-channel, the silicon substrate and the polysilicon film on the gate may be of n-type, and the diffusion layers for forming the source and drain regions may be of p-type.

発明の効果 本発明のMOS型半導体装置によれば、ゲート上にポリ
シリコン膜を設けることによb1ゲート下のシリコン基
板のチャンネルに加えて、ポリシリコン膜中にもチャン
ネルが形成できるので、ドレイン電流駆動能力の高いM
OS型半導体装置を提供できる。
Effects of the Invention According to the MOS type semiconductor device of the present invention, by providing a polysilicon film on the gate, a channel can be formed in the polysilicon film in addition to the channel in the silicon substrate under the b1 gate. M with high current drive ability
An OS type semiconductor device can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例におけるMOS型半導体装置
の断面図、第2図は従来のMOSfi半導体装置の断面
図である。 1・・・・・・p型シリコン基板、2・・・・・・酸化
膜、3・・・・・・ゲート、4a・・・・・・下部ドレ
イン領域、4b・・・・・・下部ソース領域、5・・・
・・・p型ポリシリコン膜、6a・・・・・・上部ドレ
イン領域、6b・・・・・・上部ソース領域、7a・・
・・・・nチャンネル、7b・・・・・・nチャンネル
、11・・・・・・p型シリコン基板、12・・・・・
・酸化膜、13・・・・・・ゲート、14a・・・・・
・ドレイン領域、14b・・・・・・ソース領域、17
・・・・・・nチャンネル。
FIG. 1 is a sectional view of a MOS type semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional MOSfi semiconductor device. DESCRIPTION OF SYMBOLS 1...P-type silicon substrate, 2...Oxide film, 3...Gate, 4a...Lower drain region, 4b...Lower Source area, 5...
... p-type polysilicon film, 6a ... upper drain region, 6b ... upper source region, 7a ...
...n channel, 7b...n channel, 11...p type silicon substrate, 12...
・Oxide film, 13...Gate, 14a...
・Drain region, 14b... Source region, 17
・・・・・・N channel.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上のゲートとなる第一ポリシリコン膜
上に絶縁膜を構成し、この絶縁膜上にソース領域とドレ
イン領域を有する第二ポリシリコン膜を構成することに
より、ゲートとなる上記第一ポリシリコン膜を上記半導
体基板および上記第二ポリシリコン膜で挟む構造とし、
上記半導体基板および第二ポリシリコン膜の二層部分に
チャンネルを備えたことを特徴とするMOS型半導体装
置。
(1) An insulating film is formed on a first polysilicon film that becomes a gate on a semiconductor substrate, and a second polysilicon film having a source region and a drain region is formed on this insulating film. A first polysilicon film is sandwiched between the semiconductor substrate and the second polysilicon film,
A MOS type semiconductor device characterized in that a channel is provided in a two-layer portion of the semiconductor substrate and the second polysilicon film.
(2)絶縁膜がゲートとなる第一ポリシリコン膜の表面
酸化膜であることを特徴とする特許請求の範囲第1項に
記載のMOS型半導体装置。
(2) The MOS type semiconductor device according to claim 1, wherein the insulating film is a surface oxide film of the first polysilicon film serving as the gate.
JP15344989A 1989-06-15 1989-06-15 Mos type semiconductor device Pending JPH0319285A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15344989A JPH0319285A (en) 1989-06-15 1989-06-15 Mos type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15344989A JPH0319285A (en) 1989-06-15 1989-06-15 Mos type semiconductor device

Publications (1)

Publication Number Publication Date
JPH0319285A true JPH0319285A (en) 1991-01-28

Family

ID=15562799

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15344989A Pending JPH0319285A (en) 1989-06-15 1989-06-15 Mos type semiconductor device

Country Status (1)

Country Link
JP (1) JPH0319285A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5757047A (en) * 1995-12-14 1998-05-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5757047A (en) * 1995-12-14 1998-05-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same
US5933736A (en) * 1995-12-14 1999-08-03 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device

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