JPH04267551A - Thin film transistor - Google Patents

Abstract

PURPOSE:To improve the degree of integration of a thin film transistor by reducing the areas occupied by a p-channel and n-channel transistors. CONSTITUTION:An n-channel and p-channel transistors 3 and 4 are respectively formed on the lower and upper surfaces of a polysilicon semiconductor layer 2 having a level cross shape. The transistor 3 is composed of a source and drain areas 13 and 14 which are formed on both sides along one direction of the crossing section of the layer 2, a channel area formed below the crossing section of the layer 2, etc. The transistor 4 is composed of a source and drain areas 15 and 16 which are formed on both sides along the other direction of the crossing section of the layer 3, a channel area formed on the crossing section of the layer 2, etc. The n-channel of the transistor 3 and p-channel of the transistor 4 are positioned at a certain interval in the thickness direction of the layer 2.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to thin film transistors.

0002

2. Description of the Related Art As a thin film transistor, for example, a CMOSFET used as an inverter is known. Such a thin film transistor has a structure in which a p-channel transistor and an n-channel transistor are formed side by side on the surface of a semiconductor layer, and the drain electrode of the p-channel transistor and the drain electrode of the n-channel transistor are connected.

0003

However, in such conventional thin film transistors, two transistors, a p-channel transistor and an n-channel transistor, are formed on one side of the semiconductor layer.
Since two transistors are formed side by side, the transistor occupies a large area, which limits miniaturization. An object of the present invention is to provide a thin film transistor that can be further miniaturized.

0004

[Means for Solving the Problems] The present invention is such that the channel region of each transistor is formed in a stacked manner so that a p-channel transistor is formed on one side of a semiconductor layer and an n-channel transistor is formed on the other side. be.

[0005]

[Operation] According to the present invention, since the p-channel transistor and the n-channel transistor are formed so that each channel region is stacked, compared to the case where two transistors are formed side by side on one side of the semiconductor layer, It is possible to reduce the occupied area and achieve miniaturization.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 3 show a thin film transistor according to an embodiment of the present invention. In this thin film transistor, a semiconductor layer 2 made of polysilicon is provided on the upper surface of a substrate 1 made of ceramic or the like.
It has a structure in which an n-channel transistor 3 is formed on the bottom surface of the transistor, and a p-channel transistor 4 is formed on the top surface. That is, an n-channel gate electrode 11 is formed on the upper surface of the substrate 1, and a gate insulating film 12 is formed on the surface of this n-channel gate electrode 11. A semiconductor layer 2 is formed in a planar cross shape on the upper surface of the substrate 1 including the surface of the gate insulating film 12 . An n-channel source region 13 and an n-channel drain region 14 are formed on both sides of the intersection of the semiconductor layers 2 in one direction by phosphorus ion implantation, and p-channel source regions 15 are formed on both sides in the other direction by boron ion implantation. and a p-channel drain region 16 are formed. The intersection of the semiconductor layer 2 has a thickness of, for example, about 500 to 1000 Å, and the lower n-channel region 17 and the upper p-channel region 18 do not intersect in the same plane as shown by the two-dot chain line. The structure is such that they are formed at intervals in the thickness direction.

A gate insulating film 19 is formed on the surface of the semiconductor layer 2 in a planar cross shape. A p-channel gate electrode 20 is formed on the upper surface of the gate insulating film 19 at a portion corresponding to the intersection of the semiconductor layers 2 . A contact hole 21 is formed in a portion of the gate insulating film 19 corresponding to the n-channel source region 13 and the n-channel drain region 14.
, 22 are formed, and are connected to the n-channel source region 13 and the n-channel drain region 14 through these contact holes 21 and 22, respectively.
A channel source electrode 23 and an n-channel drain electrode 24 are formed on the upper surface of the gate insulating film 19, respectively. Gate insulating film 1 in portions corresponding to p-channel source region 15 and p-channel drain region 16
Contact holes 25 and 26 are formed in the contact holes 25 and 26, respectively, and a p-channel source electrode 27 is connected to the p-channel source region 15 and the p-channel drain region 16, respectively, through these contact holes 25 and 26.
and the p-channel drain electrode 28 is connected to the gate insulating film 1.
9, respectively. The n-channel drain electrode 24 and the p-channel drain electrode 28 are
They are connected by a connection electrode 29 formed on the top surface of the substrate 1.

Next, the operation of this thin film transistor will be explained. First, as shown in FIGS. 4(A) and (B),
+VGS to the gate electrode 20 of the p-channel transistor 4
is applied to the gate electrode 1 of the n-channel transistor 3.
When +VGS is applied to the semiconductor layer 1, negative charges are attracted to the upper surface of the semiconductor layer 2 in the region facing the n-channel gate electrode 11, and an n-channel region 17 is generated. Also,
Similarly, the back surface of the semiconductor layer 2 in the region facing the p-channel gate electrode 20 becomes n-type. Therefore, in the n-channel transistor 3, a current flows through the n-channel region 17 and the transistor is turned on. On the other hand, in p-channel transistor 4, p
No current flows through the channel region 18 and it is turned off.

Next, as shown in FIGS. 5(A) and 5(B),
+VGS to the gate electrode 20 of the p-channel transistor 4
is applied to the gate electrode 1 of the n-channel transistor 3.
When −VGS is applied to 1, negative charges are attracted to the upper surface of the semiconductor layer 2 in the region facing the p-channel gate electrode 20, and this portion becomes n-type, and the n-channel gate electrode 11 Positive charges are attracted to the back surface of the semiconductor layer 2 in the region facing the region, and this region becomes p-type. Therefore, both p-channel transistor 4 and n-channel transistor 3 are turned off with no current flowing through their respective channel regions 18 and 17.

Next, as shown in FIGS. 6(A) and 6(B),
-VGS to the gate electrode 20 of the p-channel transistor 4
is applied to the gate electrode 1 of the n-channel transistor 3.
When -VGS is applied to 1, positive charges are attracted to the upper surface of the semiconductor layer 2 in the region facing the p-channel gate electrode 20, and this part becomes p-type, and the n-channel gate electrode 11 Similarly, the back surface of the semiconductor layer 2 in the region facing the p-type is made p-type. Therefore, in p-channel transistor 4, current flows through p-channel region 18 and turns on. On the other hand, n-channel transistor 3 is turned off because no current flows through n-channel region 17.

Next, as shown in FIGS. 7(A) and 7(B),
-VGS to the gate electrode 11 of the p-channel transistor 4
is applied to the gate electrode 1 of the n-channel transistor 3.
When +VGS is applied to the gate electrode 11, positive charges are attracted to the upper surface of the semiconductor layer 2 in the region facing the p-channel gate electrode 20, and this part becomes p-type, and the n-channel gate electrode 11 and Negative charges are attracted to the back surface of the semiconductor layer 2 in the opposing region, and this portion becomes n-type. Therefore, both p-channel transistor 4 and n-channel transistor 3 are turned on with current flowing through their respective channel regions 18 and 17. At this time, the thickness of the intersection portion of the semiconductor layer 2 is, for example, 500 to 1000 Å.
Since the transistors are thick to a certain extent, the n-channel and p-channel do not intersect in the same plane, and both transistors turn on independently.

[0012] Thus, in this thin film transistor,
As shown in FIG. 4, +VGS is applied to both gate electrodes 11 and 20.
is applied, p-channel transistor 4 is off and n-channel transistor 3 is on. On the other hand, as shown in FIG. 6, when -VGS is applied to both gate electrodes 11 and 20, p-channel transistor 4 is When the n-channel transistor 3 is turned on, the n-channel transistor 3 is turned off, so if the connection electrode 29 connecting both drain electrodes 24 and 28 is used as an output electrode, a CMOSFET that can be used as an inverter can be constructed. In this case, usage as shown in FIG. 7 is prohibited. Note that without connecting both drain electrodes 24 and 28 with the connection electrode 29, the p-channel transistor 4 and n
It is also possible to use each channel transistor 3 independently. In this case, usage as shown in FIG. 7 is not prohibited.

[0013]

As explained above, according to the present invention, since a p-channel transistor and an n-channel transistor are formed in a stacked manner in a semiconductor layer, two transistors can be formed on one side of the semiconductor layer. Compared to the case where they are formed side by side, the occupied area can be reduced, downsizing can be achieved, and it is also possible to achieve high integration.

[Brief explanation of the drawing]

FIG. 1 is a perspective view of a thin film transistor in an embodiment of the present invention.

FIG. 2 is a sectional view taken along line CC in FIG. 1.

FIG. 3 is a sectional view taken along line DD in FIG. 1;

[Figure 4] +VG at the gate electrode of the p-channel transistor
FIG. 3 is a diagram for explaining a state when S is applied and +VGS is applied to the gate electrode of an n-channel transistor.

[Figure 5] +VG at the gate electrode of the p-channel transistor
FIG. 4 is a diagram for explaining a state when S is applied and -VGS is applied to the gate electrode of an n-channel transistor.

[Figure 6] -VG at the gate electrode of a p-channel transistor
FIG. 4 is a diagram for explaining a state when S is applied and -VGS is applied to the gate electrode of an n-channel transistor.

[Figure 7] -VG at the gate electrode of a p-channel transistor
FIG. 3 is a diagram for explaining a state when S is applied and +VGS is applied to the gate electrode of an n-channel transistor.

[Explanation of symbols]

2 Semiconductor layer 3 N-channel transistor 4 p-channel transistor 11 Gate electrode for n-channel 13 Source region for n-channel 14 Drain region for n-channel 15 Source region for p channel 16 Drain region for p channel 17 N-channel region 18 p channel region 19 Gate insulation film 20 Gate electrode for p channel 23 Source electrode for n-channel 24 Drain electrode for n-channel 27 Source electrode for p channel 28 Drain electrode for p channel 29 Connection electrode

Claims (2)

[Claims] 1. A p-channel transistor and an n-channel transistor are provided to cross each other so that a p-channel is formed on one side of a semiconductor layer and an n-channel is formed on the other side, and the same channels are not formed in the same plane. A thin film transistor characterized in that the semiconductor layer is formed thickly. 2. The thin film transistor according to claim 1, wherein the drain electrode of the p-channel transistor and the drain electrode of the n-channel transistor are connected to form a CMOSFET.