JPS5887859A - Cmos semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable to obtain a high degree of integration for the titled device by a method wherein the layout for a CMOS inverter is contrived in such a manner that the channel length direction of the MOSFET for load and that of the MOSFET for driving make crossing at a right angle. CONSTITUTION:As the drain and the source of the MOSFET for a p-channel type load are used as p<+> regions 15 and 16 respectively, and the section between these p<+> regions 15 and 16 is used as the channel of the current located between the drain and the source, a layout is made out in such a manner that the channel direction of them will be brought in vertical direction and that the channel length direction of the MOSFET 1 and 2 will be crossed making a right angle. By making out the layout of memory cells as above-mentioned, the built- in MOSFET 1 for load can be formed in an excellent reproducibility even when the channel length of the MOSFET 2 for driving is reduced to a submicron level as the microscopic formation of the cell progresses without depending upon the accuracy of mask-matching, thereby enabling to improve the degree of integration of the CMOS inverter pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention is a CMOS (Complementary
Mccal Oxide Semiconductor)
The present invention relates to semiconductor integrated circuits, and particularly to the layout of vertical CMOS inverters that enable higher integration of CMO8 circuits.

Conventional devices of this type include those shown in FIGS. 1 to 3. Figure 1 is a circuit diagram of a cN4os inverter.
FIG. 2 is a layout diagram thereof, and FIG. 3 is a sectional view showing its structure. First, as shown in FIG.
ield Effect Transistor) (
11 and an N-channel MOS FET [2],
It is composed of an input terminal (4) and an output terminal (5). In addition, in FIGS. 2 and 3, the 111m polysilicon (11J acts as a common gate electrode for the P-channel type MOS FET t1+ and the N-channel type MOS FET (21), respectively, and The silicon (11) is connected to the input terminal (4), and the N+ diffusion layer (12), Q3) and the insulating film (17) are each an N-channel type MO formed on the semiconductor substrate (23).
It constitutes the drain, source and gate insulating films of the 5FET (2), and also the P region (15), +16+ and the insulating film (
The old and N type regions (14) are respectively P channel type M
OS FET (consists of the drain, source, gate insulating film and substrate of 1+, and one metal wiring (1ω is
The P region (19) and the N'+ diffusion layer (12) are interconnected through the contacts) E) and @, and the other metal wiring (20) is connected to the p+
The region (16) is connected to the power terminal (3) via the contact (5), and the metal wiring 21+ is connected to the contact (5).
The N+ diffusion layer (131) is connected to the ground line (6) via the N+ diffusion layer (131), and one CMOS inverter is formed with the following configuration. be.

As mentioned above, conventional CMOS inverters are composed of P-channel type MOS FET (1) and N-channel type MOS FET (1).
Since the channel length directions of E-1-(2) and E-1-(2) are the same, the load MOS 1"
The channel length of E-r (1) (distance between each element (15) +16+ in Figure 3) is determined by the MO8FET for driving.
[Channel length of 21 (each element in Figure 3 + 12)
It is necessary to make the distance between Q and l1 shorter than the distance between Q and l1.
When the channel length of FET121 was reduced to the submicron level, MO8IJ FET (1) for load
The disadvantages were that it became difficult to produce with good reproducibility and the degree of integration did not improve.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and the CMOS is designed so that the channel length direction of the load MOS type FET and the channel length direction of the drive MO5I FE-r are orthogonal to each other. The purpose of this invention is to provide a CMO8 integrated circuit that enables high integration by arranging inverters.

An embodiment of the present invention will be described below with reference to the drawings. Fourth
The figure is a pattern diagram of a CMOS inverter configured with the layout of the present invention, FIG. 5 is a sectional view taken along the line V-V in FIG. 4, and FIG. 6 is a sectional view taken along the line Vl-VI in FIG. 4. In each figure, the same numbers as in FIGS. 2 and 3 refer to the same parts.

Further, the circuits of the CMOS inverters shown in FIGS. 4 to 6 are the same as that shown in FIG. 1.

In the present invention, a P-channel type load MOS FET (1
1 channel length direction and N channel type partial movement MOS F
The difference from the conventional configuration is that the channel length directions of ET (2) are orthogonal to each other.

That is, in this example, the first layer polysilicon (11
) as a common gate electrode for each of the MOS FETs (1) and (2), an N-channel partial MOS FET (21 with drain and source are the N+ diffusion layers (12) and (13), respectively.
), so this N-channel type partial movement MOS F E
The channel length direction of T+2+ is the left-right direction in FIGS. They are laid out so that they are orthogonal, that is, P
The drain and source of channel-type load MOS FET (1) are P+ regions 0 and (15), respectively, and these P+ regions (former 09) are naturally the channel (current path between drain and source). Therefore, the layout is made so that the channel length direction is in the vertical direction in FIG. 4 (the horizontal direction in FIG. 6), and each of the MOS FETs is
The channel length directions of l +21 are orthogonal to each other.

If the memory cell is laid out in this way, even when the channel length of the driving MO8I FET (21) is reduced to the sub-micron level as miniaturization progresses, the load Mo5g FE can be used without depending on mask alignment accuracy.
'r(1) can be created with good reproducibility, and CM
The degree of integration of the OS inverter can be improved.

Note that in the CMOS inverter of the above embodiment, the P-channel type MO8FET (1) is replaced by the N-channel type MO8-FET.
E'r (It was laid out so that it overlapped with 2+,
It goes without saying that the same effect can be achieved even if the layout is upside down. In that case, the polarity of the voltage may be reversed. In addition, in the above embodiment, the load MOS F
Although the ET +1+ was laid out so as to overlap the driving MOS FET (2+), the same effect can be achieved even if the ET +1+ is laid out upside down.

As described above, according to the present invention, the vertical CMOS inverter is laid out so that the channel length direction of the load MO8FET and the channel length direction of the drive MO8P'E'l are orthogonal to each other, so that mask alignment accuracy is achieved. There is an effect that the degree of integration of the vertical CMOS inverter can be improved without depending on the vertical CMOS inverter.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional CMOS inverter, FIG. 2 is a layout diagram thereof, FIG. 3 is a sectional view thereof, FIG. 4 is a layout diagram of a CMOS inverter showing an embodiment of the present invention, and FIG. 5 is a diagram of a conventional CMOS inverter. FIG. 4 is a sectional view taken along the line ■--■, and FIG. 6 is a sectional view taken along the line Vl--Vl in FIG. (1)...First MOS FET (2)...
...Second MOSFET Note that in the drawings, the same reference numerals indicate the same or corresponding parts. Agent Makoto Kuzuno - (7) Procedural amendment (voluntary) ■, Minor case indication Patent application No. 187284 No. 1984 2
・ Title of the invention: cMos semiconductor integrated circuit 3. Relationship with the person making the amendment: Patent applicant (1) As per: “+I”+1・Zuro.

Claims (2)

[Claims] (1) First and second MOS field effect transistors (hereinafter MO8) that are complementary to each other and connected in series.
FET), the first MOSFET is stacked on top of the second MOSFET, and each MOSFET
In the CMOS inverter patterned to share gate electrodes of each of the first MOS
, a CMO5 semiconductor integrated circuit, characterized in that the channel direction of the lFET and the channel direction of the second MOSFET are laid out so as to be orthogonal to each other. (2) The CMOS semiconductor integrated circuit according to claim 1, wherein the first MOSFET has a function as a load element of a CMOS inverter, and the second MOSFET has a function as a driving element of the CMOS inverter. .