JPS56150858A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS56150858A
JPS56150858A JP5413480A JP5413480A JPS56150858A JP S56150858 A JPS56150858 A JP S56150858A JP 5413480 A JP5413480 A JP 5413480A JP 5413480 A JP5413480 A JP 5413480A JP S56150858 A JPS56150858 A JP S56150858A
Authority
JP
Japan
Prior art keywords
layer
type
gate
gate electrode
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5413480A
Other languages
Japanese (ja)
Inventor
Takashi Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5413480A priority Critical patent/JPS56150858A/en
Publication of JPS56150858A publication Critical patent/JPS56150858A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Landscapes

  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To highly integrate and accelerate the operation of a vertical ROM by serially connecting an FET having a gate electrode of the first layer and an FET having a gate electrode of the second layer so disposed that the gate electrodes of the two layers are alternately contacted with one another. CONSTITUTION:A p<+> type diffused layer 2 is formed on an n type substrate 1, and a windowlike channel region 1a is formed on the substrate. The first layer gate electrodes 5 (polysilicon) are disposed at a predetermined interval through a gate film 3 on the region 1a. The second layer gate electrode 7 is so formed as to partly superpose with the first layer gate electrode 5 covered with an insulating layer 6. The respective gate electrodes of the two layers extend to be connected to the input unit. A p<+> type diffused layer 2 is connected to a power source, an output and an earth via aluminum electrode wires 8. Since the FETs are connected serially without providing a p<+> type diffused layer between the respective gates in this manner, it can reduce the predetermined area and the floating capacity of the vertical ROM. The modes of the respective FETs can be formed in any of E type or D type by selectively introducing impurity to the substrate at the lower parts of the respective gate regions.
JP5413480A 1980-04-25 1980-04-25 Semiconductor device and manufacture thereof Pending JPS56150858A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5413480A JPS56150858A (en) 1980-04-25 1980-04-25 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5413480A JPS56150858A (en) 1980-04-25 1980-04-25 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS56150858A true JPS56150858A (en) 1981-11-21

Family

ID=12962103

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5413480A Pending JPS56150858A (en) 1980-04-25 1980-04-25 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS56150858A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0133023A2 (en) * 1983-07-29 1985-02-13 Hitachi, Ltd. Read-only memory
JPS62214594A (en) * 1986-03-14 1987-09-21 Nec Corp Semiconductor memory device
JPS63104469A (en) * 1986-10-22 1988-05-09 Hitachi Ltd Manufacture of semiconductor integrated circuit device
JPS6431456A (en) * 1987-07-27 1989-02-01 Sharp Kk Semiconductor device
EP0317136A2 (en) * 1987-11-13 1989-05-24 Hitachi, Ltd. A method of producing a semiconductor integrated circuit device
US5442209A (en) * 1992-05-30 1995-08-15 Gold Star Electron Co., Ltd. Synapse MOS transistor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5341188A (en) * 1976-08-25 1978-04-14 Hitachi Ltd Mis type semiconductor device
JPS54138383A (en) * 1978-04-20 1979-10-26 Nippon Telegr & Teleph Corp <Ntt> Semiconductor memory device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5341188A (en) * 1976-08-25 1978-04-14 Hitachi Ltd Mis type semiconductor device
JPS54138383A (en) * 1978-04-20 1979-10-26 Nippon Telegr & Teleph Corp <Ntt> Semiconductor memory device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0133023A2 (en) * 1983-07-29 1985-02-13 Hitachi, Ltd. Read-only memory
JPS62214594A (en) * 1986-03-14 1987-09-21 Nec Corp Semiconductor memory device
JPS63104469A (en) * 1986-10-22 1988-05-09 Hitachi Ltd Manufacture of semiconductor integrated circuit device
JPS6431456A (en) * 1987-07-27 1989-02-01 Sharp Kk Semiconductor device
EP0317136A2 (en) * 1987-11-13 1989-05-24 Hitachi, Ltd. A method of producing a semiconductor integrated circuit device
US5442209A (en) * 1992-05-30 1995-08-15 Gold Star Electron Co., Ltd. Synapse MOS transistor

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