JPS5756961A - Complementary mos field effect semiconductor device - Google Patents

Complementary mos field effect semiconductor device

Info

Publication number
JPS5756961A
JPS5756961A JP55131085A JP13108580A JPS5756961A JP S5756961 A JPS5756961 A JP S5756961A JP 55131085 A JP55131085 A JP 55131085A JP 13108580 A JP13108580 A JP 13108580A JP S5756961 A JPS5756961 A JP S5756961A
Authority
JP
Japan
Prior art keywords
type
region
substrate
oxidized film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55131085A
Other languages
Japanese (ja)
Inventor
Mikio Kyomasu
Kunihisa Hikita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP55131085A priority Critical patent/JPS5756961A/en
Publication of JPS5756961A publication Critical patent/JPS5756961A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To enable the increase in the mounting density and the acceleration in the operation of a semiconductor device by isolating the equal reversely conductive type floating regions to a substrate with an oxidized film and laser annealing the polysilicon layer on the respective regions, thereby forming an FET. CONSTITUTION:An N<+> type region 23 and a P<+> type region 22 are formed, for example, in an N type substrate isolated with selectively oxidized film 21, polysilicon layer 24 is accumulated on the overall surface, and is laser annealed to form single crystal. Subsequently, the region 22 on the layer 24 is formed in P type and the region 23 is formed in N type, gate oxidized film 34, 44 and gate polysilicon electrodes 35, 45 are formed, and N<+> type layers 32, 33, P<+> type layers 42, 43 to become source and drain regions are then diffused. Subsequently, aluminum wire layers 51- 53 are fored, and N-channel FETA and P-channel FETB are connected in series with each other. In this manner, a C-MOS device can be formed without providing a P- well, the circuit can be reduced in size and can be increased in mounting density, and the capacity between the drain and the substrate can be reduced, thereby accelerating the operation.
JP55131085A 1980-09-20 1980-09-20 Complementary mos field effect semiconductor device Pending JPS5756961A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55131085A JPS5756961A (en) 1980-09-20 1980-09-20 Complementary mos field effect semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55131085A JPS5756961A (en) 1980-09-20 1980-09-20 Complementary mos field effect semiconductor device

Publications (1)

Publication Number Publication Date
JPS5756961A true JPS5756961A (en) 1982-04-05

Family

ID=15049627

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55131085A Pending JPS5756961A (en) 1980-09-20 1980-09-20 Complementary mos field effect semiconductor device

Country Status (1)

Country Link
JP (1) JPS5756961A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4566025A (en) * 1982-06-24 1986-01-21 Rca Corporation CMOS Structure incorporating vertical IGFETS
US4755863A (en) * 1983-04-21 1988-07-05 Kabushiki Kaisha Toshiba Semiconductor device having a semiconductor substrate with a high impurity concentration
US5362981A (en) * 1992-01-07 1994-11-08 Fujitsu Limited Integrated semiconductor device having a buried semiconductor layer and fabrication method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4566025A (en) * 1982-06-24 1986-01-21 Rca Corporation CMOS Structure incorporating vertical IGFETS
US4755863A (en) * 1983-04-21 1988-07-05 Kabushiki Kaisha Toshiba Semiconductor device having a semiconductor substrate with a high impurity concentration
US5362981A (en) * 1992-01-07 1994-11-08 Fujitsu Limited Integrated semiconductor device having a buried semiconductor layer and fabrication method thereof
US5589410A (en) * 1992-01-07 1996-12-31 Fujitsu Limited An integrated semiconductor device having a buried semiconductor layer and fabrication method thereof

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