JPS5635436A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5635436A
JPS5635436A JP11034079A JP11034079A JPS5635436A JP S5635436 A JPS5635436 A JP S5635436A JP 11034079 A JP11034079 A JP 11034079A JP 11034079 A JP11034079 A JP 11034079A JP S5635436 A JPS5635436 A JP S5635436A
Authority
JP
Japan
Prior art keywords
type
regions
electrode
layers
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11034079A
Other languages
Japanese (ja)
Inventor
Yukimasa Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11034079A priority Critical patent/JPS5635436A/en
Publication of JPS5635436A publication Critical patent/JPS5635436A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain a high circuit density without producing any diode characteristic on the connecting path by performing the formation and connection of transistors of P and N channels on the same semiconductor substrate, through a high- melting point metal. CONSTITUTION:N type Si layers are stacked on a sapplire substrate 1 and subjected to selective etching and caused to remain as N type layers 31, 33 and 32 only in P, N, P-channel transistors 2, 4 and 3 forming regions. Then, a stepped source region consisting of P<+> type region 21a and 21b and a stepped P<+> type drain region consisting of regions 41a and 41b are diffused and formed in a layer 31 for P- channel transistor, and an N<+> type polycrystal gate electrode 61 embedded in an SiO2 film 51, is formed on the surfaces of these regions. An Al electrode 112 is fitted to the regions 21b, and the region 41b is connected to N and P channel transistors 4 and 3 similarly constructed as described above. Upon this occasion, the connection is performed by use of an N<+> polycrystal layer 62 through a metal electrode 10 such as Mo, W and Pt.
JP11034079A 1979-08-31 1979-08-31 Semiconductor device Pending JPS5635436A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11034079A JPS5635436A (en) 1979-08-31 1979-08-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11034079A JPS5635436A (en) 1979-08-31 1979-08-31 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5635436A true JPS5635436A (en) 1981-04-08

Family

ID=14533265

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11034079A Pending JPS5635436A (en) 1979-08-31 1979-08-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5635436A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57117257A (en) * 1981-01-13 1982-07-21 Nec Corp Semiconductor device
JPS58197854A (en) * 1982-05-14 1983-11-17 Nec Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57117257A (en) * 1981-01-13 1982-07-21 Nec Corp Semiconductor device
JPS58197854A (en) * 1982-05-14 1983-11-17 Nec Corp Semiconductor device

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