JPS5460867A - Manufacture of complementary insulating gate electric field effect semiconductor device - Google Patents

Manufacture of complementary insulating gate electric field effect semiconductor device

Info

Publication number
JPS5460867A
JPS5460867A JP12801677A JP12801677A JPS5460867A JP S5460867 A JPS5460867 A JP S5460867A JP 12801677 A JP12801677 A JP 12801677A JP 12801677 A JP12801677 A JP 12801677A JP S5460867 A JPS5460867 A JP S5460867A
Authority
JP
Japan
Prior art keywords
type
film
region
diffusion
drain regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12801677A
Other languages
Japanese (ja)
Inventor
Moichi Matsukuma
Toshiaki Hoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12801677A priority Critical patent/JPS5460867A/en
Publication of JPS5460867A publication Critical patent/JPS5460867A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To increase the integral density by removing the insulating film formed on the semiconductor substrate on the channel forming region, coating there the lamination film comprising the insulating film and the acid-proof film newly and then formimg the P- and N-type channel source and drain regions through diffusion with the opening provided. CONSTITUTION:P-type well region 31 is formed through diffusion to N-type Si substrate 30 with SiO2 film 32 covering over the entire surface, and film 32 is removed through etching on the soruce and drain forming regions at both channels of the complementary circuit. Then acid-proof film 34 such as Si3N4 or the like is coated there via thin SiO2 film 33 with the opening provided on the P-channel transistor forming region to form P-type source and drain regions 35 and 36 plus P<+> -type region 37 covering over region 31 through diffusion. After this, N-type guard ring 40 is provided at both sides sandwiching region 35 and 36. At the same time, N-type source and drain regions 38 and 39 of the N-channel transistor are formed through diffusion within P-type well region 31. As a result, the chip area can be reduced.
JP12801677A 1977-10-24 1977-10-24 Manufacture of complementary insulating gate electric field effect semiconductor device Pending JPS5460867A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12801677A JPS5460867A (en) 1977-10-24 1977-10-24 Manufacture of complementary insulating gate electric field effect semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12801677A JPS5460867A (en) 1977-10-24 1977-10-24 Manufacture of complementary insulating gate electric field effect semiconductor device

Publications (1)

Publication Number Publication Date
JPS5460867A true JPS5460867A (en) 1979-05-16

Family

ID=14974392

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12801677A Pending JPS5460867A (en) 1977-10-24 1977-10-24 Manufacture of complementary insulating gate electric field effect semiconductor device

Country Status (1)

Country Link
JP (1) JPS5460867A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5084185A (en) * 1973-11-27 1975-07-07
JPS50138769A (en) * 1974-04-23 1975-11-05
JPS5197388A (en) * 1975-02-24 1976-08-26 Sohogata mos denkaikokatoranjisutanoseizohoho
JPS52117589A (en) * 1976-03-30 1977-10-03 Sony Corp Manufacture for insulating gate type semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5084185A (en) * 1973-11-27 1975-07-07
JPS50138769A (en) * 1974-04-23 1975-11-05
JPS5197388A (en) * 1975-02-24 1976-08-26 Sohogata mos denkaikokatoranjisutanoseizohoho
JPS52117589A (en) * 1976-03-30 1977-10-03 Sony Corp Manufacture for insulating gate type semiconductor device

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