JPS57107068A - Complementary mis semiconductor device - Google Patents

Complementary mis semiconductor device

Info

Publication number
JPS57107068A
JPS57107068A JP55184718A JP18471880A JPS57107068A JP S57107068 A JPS57107068 A JP S57107068A JP 55184718 A JP55184718 A JP 55184718A JP 18471880 A JP18471880 A JP 18471880A JP S57107068 A JPS57107068 A JP S57107068A
Authority
JP
Japan
Prior art keywords
region
well
fet
ion implantation
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55184718A
Other languages
Japanese (ja)
Inventor
Takehide Shirato
Koichi Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55184718A priority Critical patent/JPS57107068A/en
Publication of JPS57107068A publication Critical patent/JPS57107068A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To produce CMOS devices of N channel FET featuring higher withstand voltage by a construction wherein two or more different types of regions are produced to have different concentrations on a channel stopper region formed on a P well region, and the source and drain are formed in contact with the low concentration region. CONSTITUTION:Resist coatings 5 with an opening for a region A on which a channel stopper is to be produced in high concentration is applied after the P well 4 is provided on an N-type substrate 1 to form a nitride film 3 on region for formation of an FET in order to form a boron ion implantation layer B. Next, boron ion implantation layer C is formed through the opening of a resist coatings 6 covering ends of the nitride films 3 on the P well region. Next, after forming phosphorous ion implantation layers F are formed through resist coatings 8 on the P channel region, selective oxidizing treatment is made to produce a structure having the channel stopper region consisting of a low concentration region 11 and a high concentration region 10 under separate oxide layers 9 in the P well. Consecutively, an FET having an offset drain, for example, is formed to produce a CMOS device. By such a procedure, a small, high speed circuit of higher junction withstand voltage can be produced.
JP55184718A 1980-12-25 1980-12-25 Complementary mis semiconductor device Pending JPS57107068A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55184718A JPS57107068A (en) 1980-12-25 1980-12-25 Complementary mis semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55184718A JPS57107068A (en) 1980-12-25 1980-12-25 Complementary mis semiconductor device

Publications (1)

Publication Number Publication Date
JPS57107068A true JPS57107068A (en) 1982-07-03

Family

ID=16158144

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55184718A Pending JPS57107068A (en) 1980-12-25 1980-12-25 Complementary mis semiconductor device

Country Status (1)

Country Link
JP (1) JPS57107068A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61225857A (en) * 1985-03-29 1986-10-07 Nippon Telegr & Teleph Corp <Ntt> Manufacture of complementary semiconductor device
FR2826182A1 (en) * 2001-06-15 2002-12-20 St Microelectronics Sa High voltage CMOS integrated circuit includes substrate and casing of different conductivity, and inter-casing separation regions
KR100639979B1 (en) * 1998-06-02 2006-10-31 세이코 인스트루 가부시키가이샤 Semiconductor device and method of manufacturing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61225857A (en) * 1985-03-29 1986-10-07 Nippon Telegr & Teleph Corp <Ntt> Manufacture of complementary semiconductor device
KR100639979B1 (en) * 1998-06-02 2006-10-31 세이코 인스트루 가부시키가이샤 Semiconductor device and method of manufacturing the same
FR2826182A1 (en) * 2001-06-15 2002-12-20 St Microelectronics Sa High voltage CMOS integrated circuit includes substrate and casing of different conductivity, and inter-casing separation regions
WO2002103797A3 (en) * 2001-06-15 2003-03-13 St Microelectronics Sa High-voltage integrated cmos circuit
US7012309B2 (en) 2001-06-15 2006-03-14 Stmicroelectronics S.A. High-voltage integrated CMOS circuit

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