JPS5526666A - Insulated gate type semiconductor device - Google Patents
Insulated gate type semiconductor deviceInfo
- Publication number
- JPS5526666A JPS5526666A JP9970178A JP9970178A JPS5526666A JP S5526666 A JPS5526666 A JP S5526666A JP 9970178 A JP9970178 A JP 9970178A JP 9970178 A JP9970178 A JP 9970178A JP S5526666 A JPS5526666 A JP S5526666A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- depression
- substrate
- mode transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 230000009545 invasion Effects 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 238000010276 construction Methods 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000013078 crystal Substances 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0883—Combination of depletion and enhancement field effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To materialize a speed-up of a device by providing an additional region in a depression mode transistor in mounting on a single substrate the depression and enhancement mode transistors. CONSTITUTION:An N<+>-type source region 4 and drain region 5 are provided in a P<->-type Si substrate 1, and a P<+>-type invasion region 6 is provided in the region 4 in opposition to the region 5. Subsequently, a multi-crystal Si gate electrode 3 is formed through a gate SiO2 film 2 on the substrate 1 disposed between the regions 4 and 5, to make up an enhancement mode transistor EMOST. Furthermore, utilizing commonly the region 5 for the source region, a depression mode transistor DMOST including a N<+>-type drain region 9, P<+>-type invasion region 10, gate insulated film 7 and gate electrode 8 is formed in contact with the EMOST. According to such a construction, a shallow N-type region 11 is additionally provided by an ion implanting between the regions 5 and 9 to materialize a speed-up of the DMOST used for a load element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9970178A JPS5526666A (en) | 1978-08-15 | 1978-08-15 | Insulated gate type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9970178A JPS5526666A (en) | 1978-08-15 | 1978-08-15 | Insulated gate type semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5526666A true JPS5526666A (en) | 1980-02-26 |
Family
ID=14254350
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9970178A Pending JPS5526666A (en) | 1978-08-15 | 1978-08-15 | Insulated gate type semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5526666A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4680605A (en) * | 1984-03-12 | 1987-07-14 | Xerox Corporation | High voltage depletion mode transistor with serpentine current path |
US4906588A (en) * | 1988-06-23 | 1990-03-06 | Dallas Semiconductor Corporation | Enclosed buried channel transistor |
US4943537A (en) * | 1988-06-23 | 1990-07-24 | Dallas Semiconductor Corporation | CMOS integrated circuit with reduced susceptibility to PMOS punchthrough |
US5122474A (en) * | 1988-06-23 | 1992-06-16 | Dallas Semiconductor Corporation | Method of fabricating a CMOS IC with reduced susceptibility to PMOS punchthrough |
EP2065939A3 (en) * | 2007-11-28 | 2009-10-21 | Nanker(Guang Zhou)Semiconductor Manufacturing Corp | Constant current source device and method for manufacturing the same |
-
1978
- 1978-08-15 JP JP9970178A patent/JPS5526666A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4680605A (en) * | 1984-03-12 | 1987-07-14 | Xerox Corporation | High voltage depletion mode transistor with serpentine current path |
US4906588A (en) * | 1988-06-23 | 1990-03-06 | Dallas Semiconductor Corporation | Enclosed buried channel transistor |
US4943537A (en) * | 1988-06-23 | 1990-07-24 | Dallas Semiconductor Corporation | CMOS integrated circuit with reduced susceptibility to PMOS punchthrough |
US5122474A (en) * | 1988-06-23 | 1992-06-16 | Dallas Semiconductor Corporation | Method of fabricating a CMOS IC with reduced susceptibility to PMOS punchthrough |
US5688722A (en) * | 1988-06-23 | 1997-11-18 | Dallas Semiconductor Corporation | CMOS integrated circuit with reduced susceptibility to PMOS punchthrough |
EP2065939A3 (en) * | 2007-11-28 | 2009-10-21 | Nanker(Guang Zhou)Semiconductor Manufacturing Corp | Constant current source device and method for manufacturing the same |
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