JPS6457671A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS6457671A
JPS6457671A JP10949887A JP10949887A JPS6457671A JP S6457671 A JPS6457671 A JP S6457671A JP 10949887 A JP10949887 A JP 10949887A JP 10949887 A JP10949887 A JP 10949887A JP S6457671 A JPS6457671 A JP S6457671A
Authority
JP
Japan
Prior art keywords
region
multilayer structure
film
insulating films
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10949887A
Other languages
Japanese (ja)
Inventor
Kenji Kishi
Ban Nakajima
Kazushige Minegishi
Kenji Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP10949887A priority Critical patent/JPS6457671A/en
Publication of JPS6457671A publication Critical patent/JPS6457671A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make it possible to accomplish high density and high integration of MISLSI as well as to improve the reliability and the like of an element by a method wherein the upper surface and the side face of a gate electrode excluding its contact part are coated with the multilayer structure insulating film containing an oxidation-resistant insulating film, and a silicon film is interposed between a diffusion layer and a metal or a metal silicide film. CONSTITUTION:In the semiconductor device having a plurality of MIS transistors, multilayer structure insulating films 5, 16 and 17 containing oxidation-resistant insulating films 16 and 17 are provided on the region of the upper surface of a conductive substance 6 constituting the gate electrode of the MIS transistors excluding the first region (contact part) of the surface and also on the side face of the conductive substance 6. Also, a multilayer structure conductive substance, containing a metal film or a metal silicide film 12 and a silicon film 8, is connected to the region containing the second region, the end parts of the above- mentioned multilayer structure insulating films 5, 16 and 17 and the circumference of the element isolation region 2, is connected to the region containing the second region, surrounded by the end part of the above-mentioned multilayer structure insulating films 5, 16 and 17 located on the side face of the gate electrode 6, among the source and drain region 3, and the circumference of an element isolation region 2, and the above-mentioned first region. Then, a side of said second region is formed in the length in which matching margin measurements are added to the minimum pattern measurements.
JP10949887A 1987-05-01 1987-05-01 Semiconductor device and manufacture thereof Pending JPS6457671A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10949887A JPS6457671A (en) 1987-05-01 1987-05-01 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10949887A JPS6457671A (en) 1987-05-01 1987-05-01 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS6457671A true JPS6457671A (en) 1989-03-03

Family

ID=14511779

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10949887A Pending JPS6457671A (en) 1987-05-01 1987-05-01 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS6457671A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5166771A (en) * 1990-01-12 1992-11-24 Paradigm Technology, Inc. Self-aligning contact and interconnect structure
US5552620A (en) * 1994-03-11 1996-09-03 Industrial Technology Research Institute Vertical transistor with high density DRAM cell and method of making
US5656861A (en) * 1990-01-12 1997-08-12 Paradigm Technology, Inc. Self-aligning contact and interconnect structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5166771A (en) * 1990-01-12 1992-11-24 Paradigm Technology, Inc. Self-aligning contact and interconnect structure
US5620919A (en) * 1990-01-12 1997-04-15 Paradigm Technology, Inc. Methods for fabricating integrated circuits including openings to transistor regions
US5656861A (en) * 1990-01-12 1997-08-12 Paradigm Technology, Inc. Self-aligning contact and interconnect structure
US5552620A (en) * 1994-03-11 1996-09-03 Industrial Technology Research Institute Vertical transistor with high density DRAM cell and method of making

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