JPS6473673A - Mos transistor - Google Patents
Mos transistorInfo
- Publication number
- JPS6473673A JPS6473673A JP23138287A JP23138287A JPS6473673A JP S6473673 A JPS6473673 A JP S6473673A JP 23138287 A JP23138287 A JP 23138287A JP 23138287 A JP23138287 A JP 23138287A JP S6473673 A JPS6473673 A JP S6473673A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- semiconductor substrate
- inclined plane
- drain region
- source region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To make a device fine without shortening a channel length by a method wherein a two-layer structure composed of a thin insulating film and a gate electrode is formed on the surface of a semiconductor substrate and the gate electrode and one part of a source-drain region are formed on a taper- etched inclined plane on the surface of the semiconductor substrate. CONSTITUTION:This transistor is constituted in the following manner: an inclined plane is formed by a taper-etching operation of the surface of a semiconductor substrate 1; a thick oxide film 2 is formed on this inclined plane; a device isolation operation is executed; after that, a thin oxide film 3 is deposited; a gate electrode 4 is formed; after that, a prescribed impurity, i.e. an impurity used to reverse the semiconductor substrate, is doped from a surface direction; a source region and a drain region 5, 6 are formed on both sides of the gate electrode 4. Accordingly, a channel during an operation of this MOS transistor is formed on the inclined plane; after the surface of the source region and the drain region 5, 6 has been oxidized thin, a thick protective insulating film 7 is deposited; in addition, contact openings are formed in the source region and the drain region 5, 6 and the gate electrode 4; a circuit is constituted by using a metal wiring part; as a result, an integrated circuit is formed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23138287A JPS6473673A (en) | 1987-09-14 | 1987-09-14 | Mos transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23138287A JPS6473673A (en) | 1987-09-14 | 1987-09-14 | Mos transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6473673A true JPS6473673A (en) | 1989-03-17 |
Family
ID=16922739
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23138287A Pending JPS6473673A (en) | 1987-09-14 | 1987-09-14 | Mos transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6473673A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8012819B2 (en) * | 2005-11-17 | 2011-09-06 | Samsung Electronics Co., Ltd. | Semiconductor device including gate stack formed on inclined surface and method of fabricating the same |
-
1987
- 1987-09-14 JP JP23138287A patent/JPS6473673A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8012819B2 (en) * | 2005-11-17 | 2011-09-06 | Samsung Electronics Co., Ltd. | Semiconductor device including gate stack formed on inclined surface and method of fabricating the same |
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