JPS577958A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS577958A
JPS577958A JP8209680A JP8209680A JPS577958A JP S577958 A JPS577958 A JP S577958A JP 8209680 A JP8209680 A JP 8209680A JP 8209680 A JP8209680 A JP 8209680A JP S577958 A JPS577958 A JP S577958A
Authority
JP
Japan
Prior art keywords
metal wiring
substrate
electrode
inactive region
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8209680A
Other languages
Japanese (ja)
Inventor
Tetsuzo Taniguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP8209680A priority Critical patent/JPS577958A/en
Publication of JPS577958A publication Critical patent/JPS577958A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices

Abstract

PURPOSE:To prevent the generation of a parasitic MOS transistor effect due to metal wiring by a method wherein a channel section of an inactive region is formed in MOS structure using a thin gate oxide film, and a gate electrode is employed as substrate potential. CONSTITUTION:A source and drain diffusion layer 1 is made up to a substrate 10, and the gate oxide film 6 and a polysilicon electrode 7 are built up in the inactive region. The electrode 7 and the metal wiring 8 are insulated by an intermediate insulating film 4. The polysilicon electrode 7 is given potential the same as the substrate. Accordingly, the generation of the parasitic MOS transistor effect can be prevented regardless of the potential of the metal wiring on the inactive region.
JP8209680A 1980-06-19 1980-06-19 Semiconductor device Pending JPS577958A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8209680A JPS577958A (en) 1980-06-19 1980-06-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8209680A JPS577958A (en) 1980-06-19 1980-06-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS577958A true JPS577958A (en) 1982-01-16

Family

ID=13764885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8209680A Pending JPS577958A (en) 1980-06-19 1980-06-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS577958A (en)

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