JPS5783064A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5783064A
JPS5783064A JP13552581A JP13552581A JPS5783064A JP S5783064 A JPS5783064 A JP S5783064A JP 13552581 A JP13552581 A JP 13552581A JP 13552581 A JP13552581 A JP 13552581A JP S5783064 A JPS5783064 A JP S5783064A
Authority
JP
Japan
Prior art keywords
layer
mask
depression
gate
oxidated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13552581A
Other languages
Japanese (ja)
Other versions
JPS5912028B2 (en
Inventor
Hirohito Kawagoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56135525A priority Critical patent/JPS5912028B2/en
Publication of JPS5783064A publication Critical patent/JPS5783064A/en
Publication of JPS5912028B2 publication Critical patent/JPS5912028B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To realize a high speed, high integration MOSIC by a method wherein an oxidation resistant mask is placed on a substrate covered with a high concentration reverse conductivity type layer which is selectively oxidated to separate reverse conductivity type regions and the gate structure is built by removing channel region oxidated layer. CONSTITUTION:For example, an n type substrate 1 is overally diffused with a p<+> layer 2 and, for example, a nitride mask 3 is formed on FET source and drain regions and, if necessary, on a tunnel accommodated wiring region 7. Next, after forming an oxide layer 4 at a depth establishing some distance from the p<+> layer, and the part of the oxide layer 4 between source and drain regions 2a and 2b is selectively removed with help of a resist mask 9, for example, to form a depression 5. Next, a gate film 6 is formed on the depression 5 and, after providing contact holes in the nitride mask 3, an Al electrode for example is formed, completing an IC. By this, a high concentration structure can be formed on self-alignment manner and a high speed operation is ensured because gate parasitic capacitance can be reduced to the order of the p<+> layer 2 thickness and overlapping.
JP56135525A 1981-08-31 1981-08-31 Manufacturing method for semiconductor devices Expired JPS5912028B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56135525A JPS5912028B2 (en) 1981-08-31 1981-08-31 Manufacturing method for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56135525A JPS5912028B2 (en) 1981-08-31 1981-08-31 Manufacturing method for semiconductor devices

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP4251371A Division JPS575052B1 (en) 1971-06-16 1971-06-16

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP7611783A Division JPS58218172A (en) 1983-05-02 1983-05-02 Manufacture of insulated gate type semiconductor device

Publications (2)

Publication Number Publication Date
JPS5783064A true JPS5783064A (en) 1982-05-24
JPS5912028B2 JPS5912028B2 (en) 1984-03-19

Family

ID=15153804

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56135525A Expired JPS5912028B2 (en) 1981-08-31 1981-08-31 Manufacturing method for semiconductor devices

Country Status (1)

Country Link
JP (1) JPS5912028B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5387528A (en) * 1992-07-23 1995-02-07 U.S. Philips Corporation Method of manufacturing a semiconductor device comprising an insulated gate field effect device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6381221U (en) * 1986-11-14 1988-05-28

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5387528A (en) * 1992-07-23 1995-02-07 U.S. Philips Corporation Method of manufacturing a semiconductor device comprising an insulated gate field effect device

Also Published As

Publication number Publication date
JPS5912028B2 (en) 1984-03-19

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