JPS56158482A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the diffused area and to obtain high integration, by providing the first conductive layer which is to become a contact electrode on the region wherein a diffused layer of an FET is formed, then, providing a gate electrodes which is formed so as to cover the gap in the first conductive layer by a gate film and the second conductive layer by self-alignment. CONSTITUTION:The surface of an active region 13 of a substrate 11 which is separated by an oxide film 12 is exposed. For example, a poly Si layer 14 is provided so that it is extended from source and drain regions 19 and 20 to the oxide layer 12. After the oxidizing process, a poly Si gate 17 is formed so as to cover the gap part (corresponding to a gate length 15) of the poly Si layer 14 via a gate film 16a. Then, the processes of the formation of the source and drain diffused layers 19 and 20, the deposition of an insulating layer 21, the formation of an opening part 22, and the formation of wiring layers 23 are performed. In this constitution, since the aligning margin between the patterns can be reduced and the area of the diffused region can be reduced, the highly integrated FET can be obtained. The amount of injection of the minority carriers into the diffused layers is reduced and the erroneous operation of the circuit can be prevented.