JPS56147434A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS56147434A JPS56147434A JP5185680A JP5185680A JPS56147434A JP S56147434 A JPS56147434 A JP S56147434A JP 5185680 A JP5185680 A JP 5185680A JP 5185680 A JP5185680 A JP 5185680A JP S56147434 A JPS56147434 A JP S56147434A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layers
- electrode
- electrodes
- cvd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 title 1
- 238000004544 sputter deposition Methods 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 238000002844 melting Methods 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
PURPOSE:To prevent oxidation of the substrate surface and improve the ohmic contacts of electrodes made of a high-melting metal such as Mo by a method wherein after the electrode lower layers contacting with a substrate have been formed by sputtering, the upper layers are formed by CVD. CONSTITUTION:For example, in the manufacturing process of an Mo gate type MOSIC, at the stage where a gate oxide film 12, source and drain diffused layers 13 and 14 have been formed and opening portions have been exposed, the whole surface is thinly coated with an Mo film 15 by sputtering at low temperature. Then, the Mo film 15 is selectively etched so that electrode layers 16 and 16' in the lower part are left. Subsequently, the whole surface is coated, by CVD, with an Mo film thick enough to obtain satisfactory electrical characteristics, which is then selectively etched to form an Mo gate electrode 18, source and drain electrodes 20 and 21 and a wiring layer 22. Thereby, when the sputtered film is formed, the surfaces of the diffused layers 13 and 14 are not oxidized. Accordingly, the ohmic contacts between the electrodes 20 and 21 and the diffused layers 13 and 14, respectively, can be improved.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5185680A JPS56147434A (en) | 1980-04-18 | 1980-04-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5185680A JPS56147434A (en) | 1980-04-18 | 1980-04-18 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS56147434A true JPS56147434A (en) | 1981-11-16 |
Family
ID=12898497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5185680A Pending JPS56147434A (en) | 1980-04-18 | 1980-04-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56147434A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59169129A (en) * | 1983-03-16 | 1984-09-25 | Fujitsu Ltd | Method for sputtering high-melting point metal or high-melting point metal silicide |
| JPS60249320A (en) * | 1984-05-25 | 1985-12-10 | Hitachi Ltd | Electrode wiring |
| JPS6155966A (en) * | 1984-08-27 | 1986-03-20 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH0228374A (en) * | 1988-04-20 | 1990-01-30 | Fujitsu Ltd | Diffusion barrier structure and its manufacture |
-
1980
- 1980-04-18 JP JP5185680A patent/JPS56147434A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59169129A (en) * | 1983-03-16 | 1984-09-25 | Fujitsu Ltd | Method for sputtering high-melting point metal or high-melting point metal silicide |
| JPH0414493B2 (en) * | 1983-03-16 | 1992-03-13 | Fujitsu Ltd | |
| JPS60249320A (en) * | 1984-05-25 | 1985-12-10 | Hitachi Ltd | Electrode wiring |
| JPS6155966A (en) * | 1984-08-27 | 1986-03-20 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH0228374A (en) * | 1988-04-20 | 1990-01-30 | Fujitsu Ltd | Diffusion barrier structure and its manufacture |
| JP2541657B2 (en) * | 1988-04-20 | 1996-10-09 | 富士通株式会社 | Diffusion barrier structure and manufacturing method thereof |
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