JPS55151334A - Fabricating method of semiconductor device - Google Patents
Fabricating method of semiconductor deviceInfo
- Publication number
- JPS55151334A JPS55151334A JP6018279A JP6018279A JPS55151334A JP S55151334 A JPS55151334 A JP S55151334A JP 6018279 A JP6018279 A JP 6018279A JP 6018279 A JP6018279 A JP 6018279A JP S55151334 A JPS55151334 A JP S55151334A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- region
- approx
- annealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
Abstract
PURPOSE:To obtain an electrode wire having less leakage with low contact resistance by irradiating ion on the metallic layer formed on the substrate when ohmic contacting the metallic layer in the region on the semiconductor substrate. CONSTITUTION:After forming reverse conducting type shallow diffusion region 2 to a silicon substrate 1, an SiO2 film 3 is formed, and an opening is partly formed in the film 3 on the diffused region 2. Then, an Mo film 4 is coated in a thickness of approx. 500Angstrom on the entire surface of the substrate 1, ion is then implanted with Ar to form an Mo-Si alloy layer 5 in the boundary of the Mo and the silicon. Thereafter, the Mo film 6 is further coated in a thickness of approx. 1mum thereon, and photoetched to form a wiring pattern thereon. Finally, it is annealed at 400-600 deg.C to form an electrode thereon. Since the alloy layer is not grown even if the Mo is annealed, no leakage occurs in case of shallow diffusion region 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54060182A JPS5950214B2 (en) | 1979-05-16 | 1979-05-16 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54060182A JPS5950214B2 (en) | 1979-05-16 | 1979-05-16 | Manufacturing method of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55151334A true JPS55151334A (en) | 1980-11-25 |
JPS5950214B2 JPS5950214B2 (en) | 1984-12-07 |
Family
ID=13134753
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54060182A Expired JPS5950214B2 (en) | 1979-05-16 | 1979-05-16 | Manufacturing method of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5950214B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5832415A (en) * | 1981-08-20 | 1983-02-25 | Sanyo Electric Co Ltd | Reducing method of contact resistance |
US4643777A (en) * | 1983-12-20 | 1987-02-17 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device comprising resistors of high and low resistances |
US4699690A (en) * | 1985-03-01 | 1987-10-13 | Fujitsu Limited | Method of producing semiconductor memory device |
US5210042A (en) * | 1983-09-26 | 1993-05-11 | Fujitsu Limited | Method of producing semiconductor device |
US5444024A (en) * | 1994-06-10 | 1995-08-22 | Advanced Micro Devices, Inc. | Method for low energy implantation of argon to control titanium silicide formation |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4836981A (en) * | 1971-09-13 | 1973-05-31 | ||
JPS5141957A (en) * | 1974-10-07 | 1976-04-08 | Nippon Electric Co | Handotaisochino denkyokukeiseihoho |
-
1979
- 1979-05-16 JP JP54060182A patent/JPS5950214B2/en not_active Expired
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4836981A (en) * | 1971-09-13 | 1973-05-31 | ||
JPS5141957A (en) * | 1974-10-07 | 1976-04-08 | Nippon Electric Co | Handotaisochino denkyokukeiseihoho |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5832415A (en) * | 1981-08-20 | 1983-02-25 | Sanyo Electric Co Ltd | Reducing method of contact resistance |
US5210042A (en) * | 1983-09-26 | 1993-05-11 | Fujitsu Limited | Method of producing semiconductor device |
US4643777A (en) * | 1983-12-20 | 1987-02-17 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device comprising resistors of high and low resistances |
US4699690A (en) * | 1985-03-01 | 1987-10-13 | Fujitsu Limited | Method of producing semiconductor memory device |
US5444024A (en) * | 1994-06-10 | 1995-08-22 | Advanced Micro Devices, Inc. | Method for low energy implantation of argon to control titanium silicide formation |
Also Published As
Publication number | Publication date |
---|---|
JPS5950214B2 (en) | 1984-12-07 |
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