JPH0394464A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the intrusion of a contaminant to a substrate and a gate insulating film by changing an impurity concentration profile in the depth direction of a gate electrode. CONSTITUTION:At least two or more of gate electrodes 14a, 14b having different impurity concentration profiles in the depth direction are formed onto a semiconductor substrate 11 through a gate insulating film 13. That is, the gate electrodes are shaped onto a silicon substrate through the gate insulating film having film thickness of approximately 100Angstrom , and impurity concentration in the vicinity of interfaces with the gate insulating film of the gate electrodes is 1X10<20>cm<-3> and 1X10<18>cm<-3>. Accordingly, the effective film thickness of the gate insulating film 13 is controlled by changing the impurity concentration profiles in the depth direction of the gate electrodes 14a, 14b, thus preventing the intrusion of a contaminant to the gate insulating film 13, thus improving reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to semiconductor devices, particularly highly reliable CMOS and DRAM.

(Prior Art) In a semiconductor device formed by integrating a plurality of transistors on a semiconductor substrate, the thickness of the gate insulating film of all the transistors is not the same, and the thickness of the gate insulating film is different from two or more types. There are cases.

In other words, in LSIs such as DRAMs that place emphasis on high-speed performance, hot-temperature
It is important to ensure carrier tolerance.

Therefore, the electricity given from outside! 1! There is a method to reduce the voltage inside the circuit and use it.

In this case, in order to ensure the reliability of the gate insulating film, it was necessary to create different thicknesses of the gate insulating film for the part to which an external power supply voltage is applied and the part to which the internal voltage is lowered.

As a method for forming a gate insulating film in such a semiconductor device, a method as shown in FIG. 2, for example, is known. The forming method shown in FIG. 2 is a method for forming gate insulating films of two transistors to different thicknesses, and this forming method will be explained with reference to FIG. 2.

First, for example, an insulating film 2 for element isolation is placed on a silicon substrate 1.
Formed by commonly used methods such as selective oxidation,
A region where each transistor is to be formed is formed. Thereafter, a first gate insulating film 3a is formed on the surface of the semiconductor substrate 1 (FIG. 2(a)).

Next, a resist material is applied to the entire surface, this resist material is patterned, and the resist material applied on the area where one transistor is to be formed is removed, leaving the resist material only on the area where the other transistor is to be formed. A remaining resist pattern 4 is formed.

Next, using this resist pattern as a mask, the first gate insulating film 3a exposed on the region where one transistor is to be formed is etched and removed (FIG. 2(b)).
).

Next, after removing the resist pattern 4, a second gate insulating film 3b is formed on the entire surface. At this time, the second gate insulating film 3b is formed on the first gate insulating film 3a. As a result, the first gate insulating film 3a is formed thicker than the second gate insulating film 3b. Then, gate electrodes 5a and 5b of the respective transistors are formed on the respective gate insulating films 3a and 3b (FIG. 2(C)).

Thereafter, a commonly used FET process is carried out to complete a semiconductor device consisting of transistors each having a gate insulating film of different thickness.

(Problems to be Solved by the Invention) In the above-described forming method, in the step shown in FIG. One gate insulating film 3a is removed by etching, and the surface of the silicon substrate 1 in a region where one transistor is to be formed is exposed.

At this time, contaminants such as dust and Na'' ions are leached from the resist pattern 4, and the leached contaminants enter the exposed silicon substrate 1 and the first gate insulating film that is in direct contact with the resist pattern 4. It is captured.

As a result, the characteristics of the first gate insulating film 3a and the second gate insulating film 3b formed on the silicon substrate 1 into which the contaminants have been incorporated deteriorate, resulting in a decrease in reliability. .

The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device in which gate insulating films of two or more thicknesses are formed on the same semiconductor substrate. An object of the present invention is to provide a semiconductor device with improved reliability by preventing contaminants from entering an insulating film.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides at least two impurity concentration profiles that differ in the depth direction on a semiconductor substrate via a gate insulating film. A gate electrode is formed and configured.

(Function) In the above structure, the present invention changes the thickness of the depletion layer formed in the gate electrode by changing the impurity concentration profile in the depth direction of the gate electrode.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a process sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

The semiconductor device of this embodiment is characterized in that the effective thickness of the gate insulating film is changed depending on the profile of the impurity concentration in the gate electrode.

For example, when a voltage is applied to a gate electrode formed of a semiconductor film made of polysilicon through a gate insulating film made of a silicon oxide film on a semiconductor substrate made of silicon, for example, not only the surface layer of the substrate but also the gate electrode is applied. A depletion layer is also formed near the interface between the gate electrode and the gate insulating film in the electrode. Therefore, the voltage applied to the gate electrode is applied to both the depletion layer formed in the gate electrode and the gate insulating film. Therefore, the effect of increasing the effective thickness of the gate insulating film can be obtained.

The depletion layer formed in such a gate electrode changes depending on the impurity concentration profile of the gate electrode. For example, when the gate electrode material is polysilicon, specifically, the maximum film thickness Δtox when this depletion layer functions as an oxide film is expressed as shown in the following equation.

Δtax-(εox/εs)X[(2εsX2φB)/
(QXNP)] 'Zu here, ε. , ε5 is the dielectric constant of the gate insulating film. The dielectric constant of silicon, φ8 is the fermi-potential level of silicon, q is the amount of electron charge, and NP is the impurity concentration near the gate insulating film interface of the gate electrode. In this way, the thickness of the depletion layer when it functions as a gate insulating film depends on the impurity concentration near the gate insulating film interface of the gate electrode.

Therefore, the effective maximum thickness T of the gate insulating film. X
If the thickness of the gate insulating film is tox, then TOx1t
It will be expressed as OX+Δtox.

For example, a gate electrode is formed on a silicon substrate via a gate insulating film with a thickness of about 100 A, and the impurity concentration near the interface between the gate electrode and the gate insulating film is set to, for example, I
X 10 20ctx-' and 1x10"cm
-'. In this way, the impurity concentration can be reduced to I
In a gate electrode with an impurity concentration of 1 0 20 am-', the effective maximum thickness of the gate insulating film is about 113 A, and in a gate electrode with an impurity concentration of I The maximum film thickness is 21
It will be about 6A. Therefore, it becomes possible to form transistors having two types of effective gate insulating film thicknesses on the same substrate.

Next, a method for manufacturing a transistor, which is an embodiment of the present invention described above, will be described with reference to process cross-sectional views shown in FIG.

First, an insulating film 12 for element isolation is formed on a silicon substrate 11 by, for example, a selective oxidation method that has been conventionally used.
FET formation regions having gate insulating films of different thicknesses are formed. After that, the surface is thermally oxidized using a thermal oxidation method or the like to form a silicon oxide film 13 that will become a gate insulating film.
For example, it is deposited to a thickness of about 100A (Fig. 1 (a)
)).

Next, a polysilicon film to be a gate electrode is deposited to a thickness of about 2000 Å over the entire surface by low pressure CVD or the like.

Thereafter, the deposited polysilicon film is patterned to form gate electrodes 14a . 14b. Next, a resist material is applied to the entire surface, and the applied resist material is removed so that the resist material remains only on the area where one transistor is to be formed and the area where the other transistor is to be formed is exposed. Patterning is performed to form a resist pattern 15. Next, using this resist pattern 15 as a mask, arsenic, which becomes an N-type impurity, is implanted in a self-aligned manner into the gate electrode 14a and the substrate 11 on both sides of the gate electrode 14a at an implantation energy of approximately 40 KeV and an implantation amount of 2X. 1 0”am-2
Ions are implanted and diffused under certain conditions. As a result, the gate electrode l4a is formed so that the impurity concentration near the interface with the gate insulating film 13 is approximately I x 10 ``co+-''. N becomes the source region and drain region
A ◆-shaped diffusion layer 16 is formed (FIG. 1(b)).

Next, after removing the resist pattern 15 up to that point,
Next, a resist pattern 17 covering the ion-implanted transistor is formed in the same manner as in the previous step. After that, the implantation energy was changed to about 10 KeV.
Under the condition that the injection amount was about 1 × 10 14 cm -2,
Arsenic ions are implanted in the same manner as in the previous step. As a result, the gate electrode 14b is formed so that the impurity concentration near the interface with the gate insulating film 13 is approximately I x 10 cm-'. N4 becomes the source region and drain region
A mold diffusion layer 18 is formed (FIG. 1(C)).

Next, after removing the resist pattern 17, an interlayer insulating film 19 such as a silicon oxide film is deposited on the entire surface by CVD method, and each diffusion layer 16.1 is formed on this interlayer insulating film 19.
8 and gate electrodes 14a and 14b are formed, and electrode wiring 20 is formed through these contact holes. This allows N-type FE with different impurity concentrations near the interface between the gate electrode and the gate insulating film.
T is complete (Fig. 1(d)).

Of the two FETs formed in this manner, the impurity concentration near the interface between the gate electrode 14a and the gate insulating film 13 of one FET is approximately IXIO cm-', so that the gate electrode 14a of one FET is approximately The effective maximum thickness Tox of the gate insulating film 13 in 14a is approximately 113A.On the other hand, the impurity concentration near the interface with the gate insulating film 13 of the gate electrode 14b of the other FET is I
Since it is approximately 0 l8ati-', the effective maximum film thickness T of the gate insulating film in the gate electrode 14b is as described above. X is approximately 216A.

Therefore, by changing the impurity concentration near the interface between the gate electrode and the gate insulating film, the resist material does not come into direct contact with the substrate or the gate insulating film, and two types of effective gate insulating film thicknesses can be obtained according to the embodiments of the present invention. It is possible to obtain transistors of the same conductivity type on the same substrate.

Note that the present invention is not limited to the embodiments described above, and may be a P-type transistor or a combination of P-type and N-type transistors.

[Effects of the Invention] As explained above, according to the present invention, the effective film thickness of the gate insulating film is controlled by changing the impurity concentration profile in the depth direction of the gate electrode. It becomes possible to form gate insulating films with effectively different thicknesses without using a manufacturing process in which contaminants enter the insulating film or substrate from the resist material. This prevents contaminants from entering the gate insulating film and improves reliability.

[Brief explanation of drawings]

FIG. 1 is a process cross-sectional view showing one manufacturing method for a semiconductor device according to an embodiment of the present invention, and FIG. FIG. 1, 11... Silicon substrate, 2, 12... Insulating film for element isolation, 3a... First gate insulating film 3b... Second gate insulating film, 4.15.17... Resist pattern, 5a,
5b, 14a, 14b-gate electrode, 13...gate oxide film, 16.18...diffusion layer, 19...interlayer insulating film, 20...electrode wiring.

Claims (2)

[Claims] (1) A semiconductor device characterized in that at least two gate electrodes having different impurity concentration profiles in the depth direction are formed on a semiconductor substrate with a gate insulating film interposed therebetween. (2) The semiconductor device according to claim 1, wherein the gate electrode is doped with an impurity having the same conductivity type as the source and drain regions.