JPS577947A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPS577947A
JPS577947A JP8313680A JP8313680A JPS577947A JP S577947 A JPS577947 A JP S577947A JP 8313680 A JP8313680 A JP 8313680A JP 8313680 A JP8313680 A JP 8313680A JP S577947 A JPS577947 A JP S577947A
Authority
JP
Japan
Prior art keywords
electrode
extracting
layer
source
contact holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8313680A
Other languages
Japanese (ja)
Other versions
JPS6257100B2 (en
Inventor
Shiyouji Ariizumi
Makoto Segawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8313680A priority Critical patent/JPS577947A/en
Priority to DE19813123348 priority patent/DE3123348A1/en
Priority to US06/274,197 priority patent/US4544941A/en
Publication of JPS577947A publication Critical patent/JPS577947A/en
Publication of JPS6257100B2 publication Critical patent/JPS6257100B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To form a plurality of contact holes accurately in the same process by approximately uniformalizing the thickness of an insulating layer to which the contact holes for forming electrode extracting wiring are bored. CONSTITUTION:A MOSFET consisting of a source 22, a drain 23, a gate oxide film 24 and a gate electrode 25 is made up in one region of a P type semiconductor substrate 20 partitioned by a separating layer 21 among elements. A conductor layer 26 for extracting an electrode and a wiring layer 27, thickness thereof are equal approximately, are built up on the separating layer 21. A source 28 constituting another MOSFET is formed in another region. The first insulating layer 29 is made up on these whole surface. An extracting electrode 30, one end thereof is connected to the source 22 and the other end thereof is connected to the conductor layer 26 for extracting the electrode, is built up, and the second insulating layer 31 is formed on the whole surface. The contact holes 33, 34, 35 are made up by means of the same photo-etching process and etching process.
JP8313680A 1980-06-19 1980-06-19 Semiconductor device and its manufacture Granted JPS577947A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP8313680A JPS577947A (en) 1980-06-19 1980-06-19 Semiconductor device and its manufacture
DE19813123348 DE3123348A1 (en) 1980-06-19 1981-06-12 Semiconductor chip and method of producing it
US06/274,197 US4544941A (en) 1980-06-19 1981-06-16 Semiconductor device having multiple conductive layers and the method of manufacturing the semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8313680A JPS577947A (en) 1980-06-19 1980-06-19 Semiconductor device and its manufacture

Publications (2)

Publication Number Publication Date
JPS577947A true JPS577947A (en) 1982-01-16
JPS6257100B2 JPS6257100B2 (en) 1987-11-30

Family

ID=13793781

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8313680A Granted JPS577947A (en) 1980-06-19 1980-06-19 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS577947A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4900690A (en) * 1987-09-07 1990-02-13 Oki Electric Industry Co., Ltd. MOS semiconductor process with double-layer gate electrode structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53108390A (en) * 1977-03-04 1978-09-21 Hitachi Ltd Semiconductor device and its manufacture

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53108390A (en) * 1977-03-04 1978-09-21 Hitachi Ltd Semiconductor device and its manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4900690A (en) * 1987-09-07 1990-02-13 Oki Electric Industry Co., Ltd. MOS semiconductor process with double-layer gate electrode structure

Also Published As

Publication number Publication date
JPS6257100B2 (en) 1987-11-30

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