JPS5618428A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPS5618428A JPS5618428A JP9342679A JP9342679A JPS5618428A JP S5618428 A JPS5618428 A JP S5618428A JP 9342679 A JP9342679 A JP 9342679A JP 9342679 A JP9342679 A JP 9342679A JP S5618428 A JPS5618428 A JP S5618428A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- pattern
- layer
- prescribed
- manufacture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 abstract 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 1
- 238000004544 sputter deposition Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To obtain a precise pattern of an insulating layer without performing pattern alignment by a method wherein a photo resist layer having a prescribed shape and provided on a semiconductor substrate is covered with the insulating layer and the insulating layer on the resist layer is stripped off by lift off technique. CONSTITUTION:The photo resist layer 61 having the prescribed pattern is formed on the semiconductor substrate 1 having element isolating regions 3 formed thereon, the first insulating layer 62 is formed on the entire surface of it by the sputtering method and the insulating layer 62 on the resist layer 61 is stripped off together with the resist to form the second insulating layer 8 having the prescribed pattern provided with the first insulating layer 62. By this way, the insulating layer 8 having the precise pattern can easily be formed omitting the high precision necessitating pattern alignment and a part of the etching process to obtain gate insulating layers 9 and conductive layers 10 for gate electrodes on the regions of source 5, drain 6 and channel 7.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9342679A JPS5618428A (en) | 1979-07-23 | 1979-07-23 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9342679A JPS5618428A (en) | 1979-07-23 | 1979-07-23 | Manufacture of semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5618428A true JPS5618428A (en) | 1981-02-21 |
Family
ID=14081968
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9342679A Pending JPS5618428A (en) | 1979-07-23 | 1979-07-23 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5618428A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49120584A (en) * | 1973-03-16 | 1974-11-18 | ||
JPS5394771A (en) * | 1977-01-29 | 1978-08-19 | Fujitsu Ltd | Forming method for thin film pattern |
-
1979
- 1979-07-23 JP JP9342679A patent/JPS5618428A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49120584A (en) * | 1973-03-16 | 1974-11-18 | ||
JPS5394771A (en) * | 1977-01-29 | 1978-08-19 | Fujitsu Ltd | Forming method for thin film pattern |
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