JPS6424465A - Manufacture of mesfet - Google Patents

Manufacture of mesfet

Info

Publication number
JPS6424465A
JPS6424465A JP18049787A JP18049787A JPS6424465A JP S6424465 A JPS6424465 A JP S6424465A JP 18049787 A JP18049787 A JP 18049787A JP 18049787 A JP18049787 A JP 18049787A JP S6424465 A JPS6424465 A JP S6424465A
Authority
JP
Japan
Prior art keywords
groove
layer
gate
exposed
insulating films
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18049787A
Other languages
Japanese (ja)
Inventor
Kazuo Tabuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP18049787A priority Critical patent/JPS6424465A/en
Publication of JPS6424465A publication Critical patent/JPS6424465A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To obtain easily the fine pattern of a gate electrode by a method wherein an inverted trapezoid-shaped first groove is formed partially in a high- resistance layer on a semiconductor substrate and its aperture width is made small by insulating films annexed on the groove walls of the first groove to form a gate in a second groove, whereon an operating layer just under this first groove is exposed. CONSTITUTION:A high-resistance layer 6 is etched until the surface of a contact layer 5 is exposed to form a first groove 11. This is formed into the form of an inverted trapezoid. An etching is performed selectively on the high- resistance layer until a contact layer 4 reaches to an operating layer 3 to form a second groove 12 and insulating films 14a and 14b consisting of SiO2 are formed on sidewalls 11a and 11b of the groove 11. As a result, the interval between the insulating films can be made smaller than a dimension B. A gate 16 having a gate length of a length to correspond to the interval between the films 14a and 14b is formed in the groove 12. A photo resist 17 is buried in the groove 11 and SjD2 film 7 and the layer 6 are etched using this resist 17 as a mask until the layer 4 is exposed and are removed.
JP18049787A 1987-07-20 1987-07-20 Manufacture of mesfet Pending JPS6424465A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18049787A JPS6424465A (en) 1987-07-20 1987-07-20 Manufacture of mesfet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18049787A JPS6424465A (en) 1987-07-20 1987-07-20 Manufacture of mesfet

Publications (1)

Publication Number Publication Date
JPS6424465A true JPS6424465A (en) 1989-01-26

Family

ID=16084278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18049787A Pending JPS6424465A (en) 1987-07-20 1987-07-20 Manufacture of mesfet

Country Status (1)

Country Link
JP (1) JPS6424465A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0445546A (en) * 1990-06-13 1992-02-14 Nec Corp Field-effect transistor
US5139968A (en) * 1989-03-03 1992-08-18 Mitsubishi Denki Kabushiki Kaisha Method of producing a t-shaped gate electrode
US5338703A (en) * 1992-10-26 1994-08-16 Mitsubishi Denki Kabushiki Kaisha Method for producing a recessed gate field effect transistor
US5358885A (en) * 1992-08-19 1994-10-25 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a field effect transistor with a T-shaped gate electrode and reduced capacitance
US5516710A (en) * 1994-11-10 1996-05-14 Northern Telecom Limited Method of forming a transistor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5139968A (en) * 1989-03-03 1992-08-18 Mitsubishi Denki Kabushiki Kaisha Method of producing a t-shaped gate electrode
JPH0445546A (en) * 1990-06-13 1992-02-14 Nec Corp Field-effect transistor
US5358885A (en) * 1992-08-19 1994-10-25 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a field effect transistor with a T-shaped gate electrode and reduced capacitance
US5338703A (en) * 1992-10-26 1994-08-16 Mitsubishi Denki Kabushiki Kaisha Method for producing a recessed gate field effect transistor
US5516710A (en) * 1994-11-10 1996-05-14 Northern Telecom Limited Method of forming a transistor

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